IBM, T. J. Watson Research Ctr., Yorktown Heights, NY
Integrated spiral inductors with 0.5-100nH inductance and Qs up to 40 are shown to be feasible in VLSI silicon technology. Circuit design aspects, such as a minimum inductor area and crosstalk between inductors, are addressed. A 5.5GHz SiGe VCO has û137dBc/Hz phase noise at 10MHz offset and 5.1mW when an integrated inductor with Q=40 is used.
Bell Labs., Lucent Technologies, Reading, PA
1Bell Labs., Lucent Technologies, Murray Hill, NJ
Accurate and spurious-free design of an integrated VCO resonator in GSM transceiver is demonstrated. The high-Q inductor (Q=37.5 at 1GHz) in the resonator is fabricated on high-resistivity Si substrate (>10kW-cm) and the GSM IC is flip-chip mounted on the same substrate. The VCO meets all GSM requirements. Phase noise is -142dBc/Hz at 10MHz offset from a 1.018GHz center frequency.
Philips Research Labs., Eindhoven, The Netherlands
A fully integrated 2.5GHz zero-IF receiver for wireless LAN applications with equal gain antenna diversity is described. A fully integrated VCO with a 200uW travelling-wave divider provides -112dBc/Hz phase noise at 2MHz offset.
NTT Wireless Systems Lab., Kanagawa, Japan
1NTT System Electronics Labs., Kanagawa, Japan
A 3-D Masterslice MMIC technology achieves 9dB amplification at 17GHz and 8dB-inversion-loss mixing in the 16.5-to-23GHz range, features 0.3 - 13.4um-emitter Si BJTs, has 24GHz fT and 30GHz fmax at 1V. Substrate losses are eliminated by 3D interconnections that use Al and Au ground planes and striplines separated by 5um polyimide layers.
IBM T. J. Watson Research Center, Yorktown Heights, NY
With 150GHz fT and 15ps gate delay measured at 1.5V, sub-0.1um CMOS shows potential for RF applications. A 10GHz VCO and 7GHz frequency divider are reported. fmax and high-frequency NF are affected by silicide gate resistance. Digital CMOS is well suited to high-frequency linear amplification but 1/f noise and low-operating voltage limit performance.
Center for Integrated Systems, Stanford, CA
A capacitor element using a fractal structure exploits both lateral and vertical electric field to increase the capacitance per unit area and reduce the effect of bottom-plate capacitance. A classic fractal structure is implemented with 0.5um design rules for 3x increase in capacitance per unit area. A CAD tool automatically generates and analyzes custom fractal layouts.
NTT System Electronics Labs., Kanagawa, Japan
A 10GHz resonant-tunneling quantizer uses monostable-to-monostable logic and a HEMT. A simulated 4b flash A/D converter uses resonant-tunneling multiple-valued quantizers. 10GHz sampling frequencies are predicted for InP technology using only 240 active devices. The experimental results are presented.
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