IBM Austin Research Lab., Austin, TX
A 1M-transistor 64b single-issue processor operates to 1.1GHz from 1.8V at 25oC. The 4-stage pipeline design in 0.15um Leff 6-layer-metal CMOS, implements 96 fixed-point ALU and load/store instructions from the PowerPC set, and uses full-custom dynamic circuits and supports full at-speed scan with a divide-by-16 tester interface.
Digital Equipment Corporation, Hudson, MA
Design tradeoffs for stall-control circuits in integer and floating-point queues of a 600MHz Alpha microprocessor are described. The floating-point queue stall logic uses one-hot coding to compare a queue free-entry count to an incoming instruction count and is implemented in 52.5kum2 in 0.35um Si. The integer stall queue design simplifies the free-entry comparator for a 35% area saving and <1% performance penalty.
IBM Corp., Rochester, MN
Instruction stream multi-threading improves execution time by helping hide the latency of memory accesses. This PowerPC processor uses two threads. Trading area and performance in CAM and general-purpose-registers, processor throughput is increased up to 30% for both Uni- and Multi-processor AS/400 system configurations with less than 10% increase in chip area.
Intel Corp., Hillsboro, OR
A third-implementation P6 microprocessor has 7.5M transistors in a 131mm2 die in a 0.25um process, and achieves 450MHz. Circuits operate between 1.4V and 2.2V to provide enhanced support for both mobile and servers. A 3.6GB/s back-side bus supports two L2 cache types, with up to 2MB on separate cache chips.
Digital Equipment Corp., Austin, TX
A 32b StrongArm integrates DMA and memory management units, and features a 16kB 32-way set-associative instruction cache and two 32-way set-associative data caches of 8kB and 0.5kB. In 0.35um CMOS, it operates at up to 200MHz from an internal 1.5V supply. At 200MHz, performance is 230 Drystone/MIPS. Conditional clocking and mux-latches reduce power to a maximum of 0.5W.
IBM, Burlington, VT
A dual-issue 40mm2 PowerPC 750 microprocessor in dual-Vt 0.2um CMOS technology uses copper for 6 layers of interconnect, with 0.63um lowest-layer pitch. Use of copper simplifies design analysis, and results in 30% reduction in RC delays to achieve 480MHz at 2.0V and 85oC fast process, and over 500MHz at room temperature.
Advanced Micro Devices, Inc., Sunnyvale, CA
Performance increases up to 10% due to micro-architectural improvements in the K6 microprocessor family. Floating-point instructions enhance graphics performance. A 100MHz socket 7 bus is implemented. The 80mm2 die is in 0.25um 5-layer-metal CMOS with tungsten local interconnect, a standard 3.3V I/O interface, and a 2.2V internal supply.
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