Broadcom Corp., Irvine, CA
A variable-rate IF sampled QAM receiver IC operates at symbol rates from 1 to 7MBaud in 4, 16, 32, 64, 128, 256, and 1024-QAM, incorporates a 10b A/D converter and analog PLLs for clock generation. The FEC decoder meets European DVB/DAVIC standards for digital cable-TV set top terminals and cable modem applications. The 46.9mm2 650k transistor chip uses 0.5um triple-level metal single-poly CMOS.
NEC Corp., Kawasaki, Japan
10Gb/s demultiplexer with frame detection uses Si-Ge bipolar process. Timing adjustment margin for the frame detection control is doubled by an architecture based on data shift selection. In this architecture, the accurate adjustment is required in a counter operating at 5GHz. The core circuit of IC dissipates only 1.8W with -4.5V supply.
Royal Institute of Technology, Stockholm, Sweden
1Ericsson Microwave Systems AB, Molndal, Sweden
2Hughes Research Laboratories, Malibu, CA
An asynchronous 2x2 crosspoint switch in InP-HBT technology operates at 20Gb/s with no measured errors. The eye-diagram is open at 25Gb/s. At 2V, supply current consumption is 120mA, including 50W drivers.
IBM T. J. Watson Research Ctr., Yorktown Heights, NY
1Seoul City University, Seoul, Korea
A 3.3V 20-channel parallel optical receiver achieves up to 1GB/s data transfer rate. Each channel takes dc-coupled optical input, and is driven by 250MHz clock for 500Mb/s/ch rate. The chip is fabricated in 1.2um GaAs MESFET technology.
Broadcom Corporation, Irvine, CA
A single-chip CMOS 100Base-T4 Fast Ethernet transceiver supports 100Mb/s data over CAT3, 4 and 5 UTP. It incorporates adaptive digital equalizers, digital clock recovery, 50MHz ADCs and 200MSample/s waveshaping DACs. Operation is robust over 140m of CAT3 UTP with BER<10-15. The transceiver measures 5.61x4.65mm2 and dissipates <1W from a 5V supply.
Micronix Integrated Systems, Aliso Diego, CA
1Level One Communications, Sacramento, CA
2University of California at Davis, Davis, CA
A CMOS IC implementing the 802.3 Ethernet standard at 100Mb/s data-rate uses mixed-signal techniques for transmit pulse shaping, receive adaptive line equalization, baseline wander compensation and timing recovery. The IC occupies 23mm2 in a 0.6um single-poly CMOS process and dissipates 850mW at 5V.
Go back to Table of Contents