SESSION FA10

SALON 9

HIGH-SPEED CHIP-TO-CHIP CONNECTIONS

Chair: J. Yetter, Hewlett Packard Co., Fort Collins, CO
Associate Chair: B. Bateman, MicroUnity Systems, Sunnyvale, CA

10.1 - A Process-Independent 800MB/s DRAM Bytewide Interface Featuring Command Interleaving and Concurrent Memory Operation - 8:30 AM

M. Griffin, J. Zerbe, A. Chan, W. Richardson, G. Tsang, M. Ching, Y. Li, C. Portmann, B. Stonecypher, L. Lai, K. Lee, V. Lee, D. Stark, H. Modarres, P. Batra, J. Louis-Chandran, J. Yang, T. Thrush, V. Hennon, J. Privitera

Rambus, Inc., Mountain View, CA

An 800MB/s DRAM with a byte-wide interface contains clock recovery and I/O circuitry performing across multiple DRAM manufacturers' processes. Logic enables interleaved transactions with concurrent operation. CAD tools for large-aspect merged logic/memory are discussed.

10.2 - A 640MB/s Bi-Directional Data-Strobed, Dual-Edge SDRAM with a 40mW DLL for a 256MB Memory System - 9:00 AM

C. Kim, J-H. Lee, J-B. Lee, C-S. Park, S-B. Lee, S-Y. Lee, C-W. Park, J-G. Roh, D-G. Kim, S-I. Cho

Samsung Electronics, Memory Division, Kyungki-Do, Korea

A 64Mb bi-directional data-strobed, dual-edge SDRAM has peak bandwidth of 2.56GB/s on a 64b channel, 256MB memory system at Vcc 3.3V and T=25^oC. The circuit features: 1) bi-directional data strobing to eliminate clock related skews of I/O data in a multi-module system, 2) low-power DLL with locking frequency from 40MHz to 160MHz, with fast access and minimal variations, and 3) twisted data busing with minimized loading difference.

10.3 - Source Synchronization and Timing Vernier Techniques for 1.2GB/s SLDRAM Interface - 9:30 AM

Y. Morooka, Y. Nakase, J. Choi¹, H. Shin¹ , D. Perlman²

Hyundai Electronics Industries, Co., Ltd., Kyoungki-do, Korea

¹Mitsubishi Electric Corp., Hyogo, Japan

²IBM Corp., Poughkeepsie, NY

An SLDRAM interface chip using 0.35um CMOS includes source synchronization and timing Vernier techniques and operates at 1.2GB/s data transfer rate on an emulation system board that carries several SLDRAM emulation modules.

BREAK 10:00 AM

10.4 - A 2.6GB/s Multi-Purpose Chip-to-Chip Interface - 10:15 AM

B Lau¹, Y-F. Chan¹, A. Moncayo¹, J. Ho¹, K. Huang¹, J. Wei¹, L. Yu¹, R. Tarver¹, Y. Hsia¹, R. Vu¹, K. Donnelly¹, R. Crisp¹, M. Allen², J. Salmon², J. Liu², M. Muthal³, C. Lee⁴, T. Nguyen⁴, B. Horine⁴, M. Leddige⁴

¹Rambus, Mountain View, CA

²Intel, Inc.,Folsom, CA/³Santa Clara, CA/⁴Hillsboro, OR

A 2.6GB/s megacell interfacing to single or double bytewide DRAMs or logic chips uses 0.18um to 0.35um CMOS. Special I/O circuits guarantee 800MBd/pin data rate. Microwave PC board design methodologies achieve the maximum possible inteconnect bandwidth.

10.5 - PRD-Based Global-Mean-Time Signaling for 500Mb/s Chip-to-Chip Communications - 10:45 AM

H. Tamura, K. Gotoh, H. Araki, S. Wakayama, T. S. Cheung, M. Saito, J. Ogawa, Y. Kato¹, T. Nishi², M. Kawano², M. Taguchi², T. Imamura

Fujitsu Labs. Ltd., Kawasaki

¹Fujitsu VLSI Ltd., Kasugai

²Fujitsu Ltd., Kawasaki, Japan

A chip-to-chip signaling scheme uses partial response detection (PRD) with zero-delay time delivery of a global timing reference or global mean time (GMT) clock. The driver power is reduced to 7.4mW/pin at 1Gb/s for a 2cm point-to-point connection. Fabricated GMT clock generator and PRD receivers confirm PRD operation with the GMT clock.

CONCLUSION 11:15 AM

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