The tutorials introduce attendees to the state-of-the-art in integrated circuits, and give understanding of and perspective on presentations at ISSCC. Each tutorial is on a seminal topic related to the conference and is presented by an expert member of the Technical Program Committee. The 6 tutorials run in parallel sessions on Wednesday, February 5th from 8:00AM to 3:30PM. Each tutorial is about 90 minutes. Attendees may register for up to 3 tutorials, on a first-come, first-served basis. Attendees will be contacted and informed as to the time of their sessions. A ticket, required for admission to each tutorial, will be included in the ISSCC registration packet.
Practical Design for Analog Discrete-Time Processing (ADTP)
Introduction to the operating principles of basic circuits for discrete time analog processing. Design and analysis techniques for the practical applications to CMOS switched-capacitor circuits, including SD modulators, algorithmic ADCs, and switched-capacitor filters. Issues of psrr, noise, charge injection, amplifier topology, and digital noise interference.
Instructor: Donald Kerth, Crystal Semiconductor, Austin, TX, received the BSEE from the University of Illinois in 1982 and MSEE from Stanford in 1983. From 1982 to 1985, he was a member of the Technical Staff at AT&T Bell Labs, Reading, PA, designing analog CMOS telecommunication devices. In 1985 he joined Crystal Semiconductor Corp., Austin, TX, developing self-calibrated and oversampling converters for industrial and seismic measurements and for communications. A Crystal Semiconductor Fellow, he holds 15 US patents.
Clock and Data Recovery for Serial Digital Communications (CR)
Techniques for data transmission over serial optical and electrical links. The common distortions that occur over such links. Eye diagrams, jitter tolerance, jitter transfer function, and jitter generation. Data encoding for run length control, framing, and dc-balance. Clock recovery for monolithic implementation including PLL components such as data-driven phase/frequency detectors and charge pumps.
Instructor: Richard Walker holds a BS in Engineering and Applied Science from Caltech, and an MS in Computer Science from California State University, Chico. Since 1981, he has been with Hewlett-Packard Labs, where he specializes in phase-locked loops for gigabit-rate data recovery. He holds 9 US patents.
Microprocessor Architecture: RISC Evolution into Super-Scalars (uP)
Guiding principles of modern microprocessor architecture. Basis of RISC architecture and relation to micro-architecture and pipelining for high-performance implementation. The next step, super-scalar implementations, is explained with respect to performance and difficulties of implementation. The super-scalar pipeline is contrasted to vector and VLIW machines.
Instructor: Vojin Oklobdzija, UC Davis, CA and Integration, Berkeley, CA, holds PhD from UCLA in 1982 and for 8 years was research staff member at IBM T.J. Watson Research Center, working on RISC architecture. From 1988-90 he taught at Univ. of California, Berkeley. He consults with Integration, Berkeley, is Professor at Univ. of California, Davis, and an IEEE Fellow.
New DRAM Architectures (DRAM)
Semiconductor and computer system trends explain the current explosion in number of DRAM architectures and fundamental challenges facing system and DRAM designers at 256Mb and 1Gb densities. Technical and business strengths and weaknesses of: EDO DRAMs, SDRAMs, RDRAMs, SLDRAMs, and MDRAMs.
Instructor: Steven Przybylski is a consultant who provides technical analysis, strategic marketing and business planning services to both semiconductor and computer systems vendors with an emphasis on the comparative analysis of the new DRAM architectures. He is the author of New DRAM Technologies: A Comprehensive Analysis of Architectures.
Making MEMS Real: Beyond the Microstructure (MEMS)
Brief overview of micromachining technologies and sensing mechanisms. Circuit architectures and associated performance limitations of IC/sensor interface. Interfacing of micromachined capacitive accelerometers, including S/N ratio vs. power dissipation analysis. Challenges facing the IC designer of MEMS.
Instructor: Jean-Paul Bardyn, CSEM, Neuchatel, Switzerland, received the PhD from University of Lille in 1990. His research was on ultra-low-noise CMOS amplifiers. He was a research assistant at ISEN (France) and Technical Director and co-founder of Mixed Silicon Structures S. A. (France). He is Deputy Head and Technical Director at CSEM, IC Design Unit, Neuchbtel. His interests are low-power mixed-signal and sensor-interface ICs.
Circuit and Technology Trends for Low-Power/High-Performance DSP (DSP)
Reduced-swing bus drivers. Embedded (variable) power supply systems: system architecture, asynchronous vs. synchronous, high-efficiency variable voltage dc-dc conversion and voltage quantization, averaging, and algorithm design. Low-voltage (<1V) high-speed: multiple-threshold CMOS, substrate biasing, dual-gate SOI and dynamic threshold CMOS.
Instructor: Anantha Chandrakasan, MIT, Cambridge, MA, received the PhD in EECS from U. C. Berkeley in 1994, and has been the Analog Devices Career Development Assistant Professor of Electrical Engineering at MIT since Sept., 1994. His interests ultra-low-power DSPs, low-voltage circuits, wireless systems, and CAD tools. He is co-author of Low Power Digital CMOS Design.
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