A 1V DSP chip for wireless communication applications incorporates architectural, circuit, and process features enabling 60MHz operation at 1.0V with a power-performance metric of 0.21mW/MHz. It is implemented in 0.25um dual-VT CMOS.
This low-power adaptive equalizer implements two 64-tap FIR filters configured in parallel as in-phase and quadrature filters. The chip dissipate 975mW at 80MHz with a 3.3V supply in 0.5um CMOS. This corresponds to 13.1mW per tap multiplier at 80MHz.
A 0.8um CMOS signal processor combines a low-noise analog front end, 16b 3us ADC/DAC, and 16b fixed-point DSP core tailored for IIR filters up to 46th order, with 80dB total SNR. For A/D/A conversion and 20th order filtering at 110kSample/s, power consumption is 25mW at 2.7V. The 20.6mm2 chip is packaged in a 20-pin TSOP.
The oversampling A/D and D/A converters of this hearing aid IC have 80dBA and 93dBA dynamic range, respectively. The digital sound processing offers versatility in filtering and AGC functions. An infrared remote control programs the IC. Few external components are needed. The is 35mm2 chip is in low-threshold 0.8um CMOS.
A matched filter (MF) for a DS-CDMA baseband calculates the correlation between an input analog signal and a PN code with a length of up to 128b at 50MHz. The MF has process-fluctuation compensation circuitry for accurate analog processing. The 7.5x7.0mm2 chip in standard 0.8um CMOS dissipates 170mW at 50MHz with a 3V supply.
A low-power digital filter for decimation and interpolation in oversampled data converters uses an approximate filtering technique. One pair of decimation filters and two pairs of interpolation filters occupy 8.02mm2 in 0.5um CMOS. Power reduction is 36% for decimation and 17% for interpolation.
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