A programmable IF amplifier is part of a 900MHz CMOS RF transceiver for GSM. The three-stage amplifier has 55dB maximum gain and is programmable in 2dB steps over an 80dB range.
A vector modulator for applications such as GMSK uses 0.6um CMOS technology and dissipates 90mW. Phase modulation is by multiplexing the outputs of a multiphase 4x8 array oscillator phase-locked to a reference. A current-mode variable-gain output driver provides 8 levels of amplitude control. The chip is 2800x2700um2.
A silicon bipolar logarithmic/limiting amplifier has a waveform-dependent current phase shifter to compensate output voltage phase shifts. Layout techniques minimize substrate cross-talk. The received-signal-strength indicator has 60dB dynamic range, and limited-output phase deviation is <7 degrees at 2GHz. The IC dissipates 250mW at 3V.
Standards are emerging for power line carrier modems (PLC) to remotely monitor and control power distribution networks. The analog interface of a PLC modulator/demodulator is in a 0.5um mixed analog/digital CMOS technology. The receive dynamic range is 105dB in the 9-95kHz frequency band. Power dissipation is 65mW at 3V.
A two-chip set supports data rates of 10-85Mb/s and contains AGC, tunable matched filters, fully integrated VCOs, ADCs, digital demodulation and forward error correction. The output is MPEG data compliant with the Digital Video Broadcast (DVB) standard. The bipolar chip dissipates 525mW at 5V and the 0.6mm CMOS chip dissipates 1.3W at 5V.
A BiCMOS quadrature oscillator-mixer IC for direct-conversion satellite receivers has 0.9-2.2GHx tuning range. LO leakage is -70dBm, I/Q phase matching is 0.5 , amplitude matching is 0.1dB, and dynamic range is 110dB. Power dissipation is 100mW at 5V.
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