A 32kx16 test chip in a 0.5um, single-poly, 3-layer-metal process has a 33um2 cell in a non-back biased process using a planar single-transistor 23fF cell. Two sets of sense-amps per memory bank allow sequential inter-bank page accesses with no penalty in data rate.
Charge-transfer pre-sensing used with a 0.8V array employing VCC bit line precharge increases read-out voltage 5x with a 40% improvement in sensing speed. A non-reset row block control enables a reduction of data retention current to 25% that of conventional circuits in a 32Mb 6.5x7.0mm2 test device fabricated in 0.25um CMOS.
A 16Mb SOI-DRAM achieves 46ns RAS access time at 1V. Body potential of SOI transistors in the array and the periphery are dynamically changed so that transistors are controlled to be partially or fully depleted. The 17.5x8.8mm2 device in 0.5um CMOS/SIMOX and has a 3.78um2 cell.
An on-wafer BIST incorporates a 4kb very-long word bus to probe the array circuits. Test results are compressed by on-wafer test management circuits resulting in wafer test time less than 1/100 that of a bit-by-bit test. The 29.52x18.39mm2 device in a 0.16um CMOS technology has a 0.4x0.8um2 cell.
A 256M SDRAM uses a 0.28um, 3-poly, 3-metal, triple-well CMOS process with a 14.91x22.01mm2 die incorporating a 0.564x1.128um2 cell. The digital DLL adds a 0.1% die area penalty with 10mW additional power dissipation at 200MHz operating frequency while providing stabilized 1ns clock access and 0ns data hold time.
A 4Gb DRAM including 2G physical memory cells using 4-level storage occupies a 986mm2 die in a 0.15um triple well CMOS process with a 0.23um2 cell using a hierarchical bit-line architecture with charge-coupled sensing and charge-sharing restore.
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