A foveated CMOS 10k transistor imager has focal plane target acquisition and tracking circuitry. A fovea of 9x9 pixels computes velocity (for smooth pursuit), while the 17x19 periphery locates the centroid (for acquisition) of a moving target. The system is used to point cameras in a 5 to 6 order dynamic range of ambient light, with minimum contrast of 10-20%, and 2D target velocity from 0.4 8.5k pixel/s.
A real-time analog VLSI chip in 2um CCD/BiCMOS estimates the focus of expansion (FOE) of a motion sequence from measured time-varying images. The 9.2x7.9mm2 IC contains a 64x64 interline CCD imager, supports 30Frame/s, and has 170mW peak power dissipation.
A 0.8um CMOS test circuit based on PWM A-D merged architecture realizes 0.1GOPS with 10ns resolution. The test chip demonstrates 14MOPS/mm2. The IC contains 8b 8-dimensional 3-row distance calculation cell arrays, 3 charge-packet-counting circuits, and a 3-input WTA circuit.
A CAM using multi-level storage has pairs of flash cells to compute Manhattan distance in analog. The chip contains 256k charge-domain- computing nodes, organized in 4k rows of 64 synapses each and performs 55GCPS at 195mW in 14x14mm2. The 32-valued cell measures 70.4um2 in 0.7um flash CMOS.
A non-volatile CAM cell with 2 transistors compares a 4-valued input pixel with a 4-valued template pattern by a combination of threshold operations and logic-value conversions. Estimated processing performance of a 1Mb CAM is 3.75TIPS while dissipating 6W from 5V. The 10.2x8.7mm2 chip is in a 0.8um EEPROM double-poly triple-metal process.
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