DISCUSSION SESSIONS

TE4 - What DRAM Architecture will Succeed the Synchronous DRAM? -- (Salon 1 - 5)

Moderator: Nicky Lu, Etron, Hsinchu, Taiwan, ROC
Organizer: Hyung-Kyu Lim, Samsung, Kyungi, Korea
Co-Organizer: Bill Martino, Motorola, Austin, TX

System memory performance is not determined solely by the latency of the individual memory components. Performance bottlenecks are encountered in PC boards and modules as the memory size increases. Recently, many new DRAM architectures have been proposed to solve the scalability problem of systems designed using SDRAMs. Economics, system performance requirements, expandability, and ease of use will determine which of these protocols best serves the needs of future high-performance multi-media PCs, and when SDRAMs will be replaced.

Panel:

Yukio Fukuzo, NEC, Kanagawa, Japan
Holger Goebel, Siemens, Munich, Germany
Craig Hampel, Rambus, Mountain View, CA
Chang-Hyun Kim, Samsung, Kyungki, Korea
Pete MacWilliams, Intel, Hillsboro, OR
Desi Rhoden, VLSI, Tempe, AZ
Bill Vogley, Texas Instruments, Houston, TX


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