Next-generation disk drive read channel ICs will require sophisticated signal processing, equalization and detection at >200MB/s rates. BiCMOS analog-oriented architectures have been faster and lower-power. Digital-intensive architectures, with an ADC followed by a DSP, can offer advantages in time-to-market, algorithm flexibility, testability, and compatibilitiy with submicron digital CMOS processes. What happens when CMOS must use 3V supplies? Is the ability to integrate digital functions an advantage? Which techniques will produce cost-effective solutions which meet the market requirements?
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