Flash memory endurance is improved to 1M cycles using circuit techniques that exploit the relationship between the source junction band-to-band current and erase gate current. The high initial erase field is eliminated. Erase time degradation is improved 2.5 times over conventional techniques.
An 86.6mm2 16Mb non-volatile memory is DRAM-compatible except for an extended RAS precharge time after write. The device can be used as an execute-in-place memory while sharing the same data bus with DRAMs. 63ns tRAC, 21ns tAA, and 11ns tCAC are achieved using 0.5um CMOS technology with a 2um2 cell.
A 3.3V color palette SRAM uses 0.5um CMOS. The port-swap architecture realizes asynchronous single bitline read/write reducing memory cell size by >24%.
A two-port 16kB cache macro uses 0.35um four-level-metal CMOS. The two-port cache utilizes a single-port, 6-device 21.67um2 SRAM memory cell with a hierarchical bit-line architecture to achieve 285MHz operation and a 2ns access time.
A 145mm2 4Mb SRAM using an 18.77um2 cell and organized as 128kx36 or 256kx18, achieves 4.7ns flow-through access using self-resetting, low-voltage-swing circuits. A voltage regulator supplies internal 2.5V with 1.4mV/deg temperature coefficient to compensate for performance degradation.
A 132mm2, 4Mb pipelined cache SRAM with 12.77um2 cell achieves 2GB/s bidirectional I/O. Controlled impedance push-pull output drivers and minimum-transition encoding reduce bus noise and power. Source resetting and bitline self equalization allow 3.5ns core access time.
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