SESSION SA20

SALON 9

CLOCKING AND I/O

Chair: G. Gerosa, Motorola, Austin, TX
Associate Chair: W. Bowhill, Digital Equipment, Hudson, MA

20.1 - A 0.35um CMOS 3MHz to 880MHz PLL 2/N Clock Multiplier and Distribution Network with Low Jitter for Microprocessors - 8:30 AM

I. Young, M. Mar, B.Bhushan Intel Corp., Hillsboro, OR

A PLL clock generator and distribution network minimizes long-term and cycle-to-cycle short-term jitter for microprocessor clocking up to 440MHz at 2.8V supply, with 83ps measured jitter, and has 880MHz VCO with a 50% duty cycle signal output and functions to 1V supply.

20.2 - A Semi-Digital Delay-Locked Loop with Unlimited Phase- Shift Capability and 80kHz to 400MHz Operating Range - 9:00 AM

S. Sidiropoulos, M. Horowitz Stanford University, Stanford, CA

A dual-loop, interpolating DLL has 12ps rms jitter, 0.44ps/mV supply sensitivity, unlimited phase , and four orders of magnitude frequency range. In 1um drawn CMOS, the circuit occupies 0.8mm2 and dissipates 102mW at 250MHz from a 3.3V supply.

20.3 - Digitally-Controlled PLL with Pulse Width Detection Mechanism for Error Correction - 9:30 AM

J. Cho Cyrix Corp., Richardson, TX

A pulse-width-detection mechanism allows a process-independent, digitally-controlled PLL to achieve low jitter and deterministic error correction. A prototype, built using 0.25um (Leff) CMOS, operates from 45MHz to 400MHz. At 250MHz, it dissipates 10mW and has peak-to-peak jitter of 315ps with 2MHz, 2V supply noise.

BREAK 10:00 AM

20.4 - A 1GHz Dual Loop Microprocessor PLL with Instant Frequency Shifting - 10:15 AM

R. Bhagwan, A. Rogers1 Sun Microsystems, Mountain View, CA 1Analog Bits, Palo Alto, CA

A PLL microprocessor clock generator with instantaneous frequency shifting for energy management and testing operates to 1GHz at 1.6V. Dual loop architecture ensures a 50% duty-cycle. The oscillator control and filter capacitor simulated PSNR is 1ps for 20mV at 500MHz.

20.5 - Clock-Powered Logic for a 50MHz Low-Power RISC Datapath - 10:45 AM

N. Tzartzanis, W. Athas University of Southern California, Marina del Rey, CA

A 16b 0.8um CMOS energy-recovery microprocessor datapath dissipates 48mW at 53MHz down to 960uW at 10MHz when powered from a resonant clock driver. Dissipation is 3 to 7 times lower than that of a conventional clock driver under the same test conditions. CMOS logic includes bootstrapped clock buffers, precharging, and pass-transistor logic.

20.6 - I/O Family with 200mV to 500mV Supply Voltage - 11:15 AM

M. Hedberg, T. Haulin Ericsson Telecom AB, Stockholm, Sweden

A family of cells with 0.2V to 0.5V I/O supply allow direct communication between circuits with VDD ranging from 5V to <1V. Implementations are in six gate array families and two custom circuits from three ASIC vendors in 0.8um to 0.35um technology. Full link power dissipation is 7.5mW at 800Mb/s in 0.5um technology.

20.7 - Partial Response Detection Technique for Driver Power Reduction in High-Speed Memory-to-Processor Communications - 11:45 AM

H. Tamura, M. Saito, K. Gotoh, S. Wakayama, J. Ogawa, Y. Kato, M. Taguchi, T. Imamura Fujitsu Labs, Atsugi, Japan

Partial-response detection cuts driver power by up to 90% in memory-to-processor communications. Detection is with auto-zero CMOS comparator combined with smaller drivers and a transmission line with damping resistors. Measured power dissipation is 12mW/pin and 3.5mW/pin at 500Mb/s and 100Mb/s, respectively, in a 0.35um CMOS DRAM process.

CONCLUSION 12:15 PM

Go back to Table of Contents