A 32b ALU using 0.3um SOI/CMOS attains 200MHz 2mW operation at supply voltages down to 0.5V. The power-delay product is 1/20 that of a conventional 3.3V 0.3um CMOS ALU. Gate-body connected SOI pass gates and body bias controlled buffers are used.
A 2V 0.35um 220k-gate SOI/CMOS gate array operates at 65% less power than conventional 3.3V bulk/CMOS. Cell structure is optimized not only to control back bias of partially-depleted SOI transistors but also to be compatible with conventional design methodologies.
Gate-over-driving CMOS architecture boosts the internal supply voltage to 0.75V for sections of logic circuits with relatively small load capacitances. This enables a reduced external 0.5V supply for solar cells. Gate delay is 1/2 and power consumption is 1/15 compared with conventional architecture.
A double gate-driven MOSFET technique built with standard CMOS technology uses dynamic threshold adjusted MOSFETs to enhance switching speed and reduce power dissipation, and is suitable for wide supply voltage range. A ring oscillator in 1.2um technology is 3x faster than a conventional design at 1V supply and has 10x reduction in leakage current.
A RF identification (RFID) tag IC is powered from a 2.45GHz RF field. The 1um CMOS analog circuits minimize power. The tag works at distances exceeding 1m. The chip power usage at maximum range is 5uW. The data recovery circuit has 1MHz bandwidth.
A 0.5um CMOS circuit with an on-chip magnetic interface provides power and communication for contactless smart card applications. A 2mm2 chip operates under magnetic fields <15 Gauss for close contactless coupling with a 4.9MHz carrier and 9600b/s data rate.
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