SESSION FP16
SALON 10-15
VIDEO AND MULTIMEDIA SIGNAL PROCESSING
W. Gass, Texas Instruments, Dallas, TX
Y. Ooi, NEC, Kawasaki, Japan
16.1 - I.McIC: A Single-Chip MPEG2 Video
Encoder for Storage - 1:30 PM
A. van der Werf,1, F. Br ls1, R. Kleihorst1, E. Waterlander1,
M. Verstraelen1, T. Friedrich2
1Philips Research Labs, Eindhoven, The Netherlands
2Philips Semiconductors Systems Lab., Hamburg, Germany
An MPEG2 SP@ML video encoder for consumer storage applications supports recursive
motion estimation. It has a programmable buffer-controller and a temporal
noise-reduction stage. The 186mm2 4.5M-transistor chip in 0.5u CMOS consumes 2.1W at
3.3V at 27MHz clock. External 4x4Mb 60ns DRAM can be shared with an MPEG2 decoder.
16.2 - A 1.5W Single-Chip MPEG2 MP@ML Encoder with Low-Power Motion Estimation and
Clocking - 2:00 PM
M. Mizuno, Y. Ooi, N. Hayashi, J. Goto, M. Hozumi, K. Furuta, Y. Nakazawa, O.
Ohnishi, Y. Yokoyama, Y. Katayama, H. Takano, N. Miki1, Y. Senda, I. Tamitani, M.
Yamashina
NEC Corporation, Kawasaki, Kanagawa, Japan
1NEC Microcomupter Technology, Kawasaki, Kanagawa, Japan
A 12.45x12.45mm2 3.1M-transistor MPEG2 video encoder chip in 0.35um three-layer-metal
CMOS uses two low-power schemes, adaptive search area motion estimation and demand
clocking, Power consumption is 1.5W at 3.3V with a 54MHz internal clock. The
fully-digital PLL has 50ps resolution for external 81MHz SDRAM clock.
16.3 - A 2.2GOPS Video DSP with 2-RISC MIMD, 6-PE
SIMD Architecture for Real-Time MPEG2 Video Coding/Decoding
- 2:30 PM
E. Iwata, K. Seno, M. Aikawa, M. Ohki, H. Yoshikawa, Y. Fukuzawa, H. Hanaki, K.
Nishibori, Y. Kondo, H. Takamuki, T. Nagai, K. Hasegawa, H. Okuda, I. Kumata, M.
Soneda, S. Iwase, T. Yamazaki
Sony Corporation, Shinagawa, Tokyo, Japan
A 2.2GOPS programmable video codec in 0.4um triple-metal CMOS handles real-time MPEG2
MP@ML encoding/decoding except motion estimation. The 14.43x14.75mm2 chip contains
3.79M transistors. It operates at 3.3v at 81MHz. Glitch preventive Booth multiplier
and column-selective-wordline SRAM reduce power consumption.
BREAK 3:00 PM
16.4 - A Real-Time MPEG2 Main Profile,
Main Level Motion Estimator Chipset - 3:15 PM
R. Pacalet, A. Lafage, N. Darbel, P. Tychon1, A. Bellier1, C.Dejean1,
C. Dutein1, E. Fert1, S. Haas1, S. Labert1, B. Lievre1, L. Simon1,
J. Talayssat2
Ecole Nationale Superieure des Telecommunications, Paris, France
1Laboratoires d'Electronique Philips, S.A.S., Limeil-Brevannes, France
Two 0.5um CMOS chips handle real-time MPEG2 MP@ML hierarchical motion estimation,
video capture, host interface, 3:2 pull down, formatted video output, filtering, and
external memory management. The 3.3V devices integrate 700k and 2.16M transistors on
8.54x7.94mm2 and 14.72x14.6mm2 dies consuming 0.3W and 3.5W respectively. Motion
estimation range is +/-192 x +/-96.
16.5 - A 400MPixel/s IDCT for HDTV by
Multibit Coding and Group Symmetry - 3:30 PM
J-R. Choi, W-J. Hur, K-K. Lee
LG Electronics Research Center, Seoul, Korea
An IDCT decompresses HDTV pictures at 400Mpixel/s. It integrates 237k transistors on
a 24mm2 die in 0.6um 3-layer-metal CMOS. The chip consumes 0.9W at 3.3V at 54MHz
clock. Radix-two multibit coding and group symmetry of the matrix multiplication
coefficients reduce complexity.
16.6 - An 80mm2 MPEG2 Audio/Video Decode LSI - 3:45 PM
Y. Okada, T. Nakamoto, H. Gunji, M. Hase, M. Oku, Y. Tsuboi, H. Mizosoe, K. Imazawa,
T. Saito, P. Del Vecchio1, S. Cismas1, K. Monsen1, G. Haber1, K. Chan2
Hitachi, Ltd., Tokyo, Japan
1CompCore Multimedia, Inc., Santa Clara, CA
2Hitachi Micro Systems, Inc., San Jose, CA
A dedicated MPEG-2 MP@ML audio/video decoder requiring <100MB/s memory bandwidth for
real-time operation integrates 135k standard-cell gates and 33kb SRAM on a 8.6x9.3mm2
die in 0.5um three-layer-metal CMOS. It consumes 1W at 3.3V at 54MHz clock.
16.7 - A 2V 250MHz Multimedia Processor - 4:15 PM
T. Yoshida, Y. Shimazu, A. Yamada, E. Holmann, K. Nakakimura, H. Takata, M. Kitao, T.
Kishi, H. Kobayashi, M. Sato, A. Mohri, K. Suzuki, Y. Ajioka, K. Higashitani
Mitsubishi Electric Corp., Itami, Japan
A 2V 250MHz dual-issue VLIW processor has sub-word and DSP instructions for
multimedia applications such as real-time MPEG2 video processing. It integrates a
300k-transistor 8mm2 core, 32kB instruction, and 32kB data RAMs on a 6.0x6.2mm2 chip
in a 0.3um four-layer-metal CMOS process.
16.8 - 23GOPS Programmable Systolic Array DSP for
Video Signal Processing - 4:45 PM
J. Yano, J. Miyake, M. Urano, G. Inoue, S. Tsubata, K. Ninomiya, K. Sokawa, Y. Miki,
K. Onizuka1, R. Itoh1, H. Nabatani, T. Nishiyama, S. Yamaguchi
Matsushita Electric Industrial Co., Ltd., Moriguchi, Osaka, Japan
1Matsushita Research Inst., Tokyo, Japan
A programmable systolic array for real-time video signal processing performs 23GOPS
with 90 video processing elements at 129.6MHz clock. The 4M-transistor die is
13.6x13.1mm2 in 0.35um three-metal-layer CMOS. It consumes 7W at 3.3V. Real-time HDTV
(MUSE) signal processing can be realized with three chips.
16.9 - A Fully-Parallel Vector Quantization Processor for
Real-Time Motion Picture Compression - 5:00 PM
T. Shibata, A. Nakada, M. Konda, T. Morimoto, T. Ohmi, H. Akutsu1, A. Kawamura2, K.
Marumoto2
Tohoku University, Sendai, Japan
1DOME, Inc., R & D Division, Tokyo, Japan
2Rohm Co., Ltd., Kyoto, Japan
A 3.3V 33MHz vector quantization chip handles 256-vector code book with 500ns search
time. It measures 7.98x9.03mm2 and integrates 800k transistors in a 0.6um
three-layer-metal CMOS technology. An eight-chip configuration with 2k-vector search
allows real-time encoding of a full-color 640x480-pixel image in less than 30ms.
CONCLUSION 5:15 PM
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