SESSION FP15

SALON 9

SERIAL DATA COMMUNICATIONS

Chair: N. Yousefi, Broadcom Corp, Irvine, CA
Associate Chair: E. Murthi, Philips Semiconductor, Sunnyvale, CA

15.1 - A 1.0625Gb/s Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis - 1:30 PM

A. Fiedler, R. Mactaggart, J. Welch, S. Krishnan LSI Logic Corp., Milpitas, CA

A Fibre-Channel-compliant 1.0625Gb/s serial interface core combines a complete transceiver, integrating data serializaton, clock/data recovery and at-speed self-test functions. The 0.5um CMOS core occupies <4mm2, and consumes 0.42W.

15.2 - A 3.3V 51.84Mb/s 16-CAP Transceiver for ATM-LANs - 2:00 PM

M. Yamaguchi, Y. Nishida, T. Muraoka, H. Yamane, H. Kariya, T. Kohno, T. Narisawa, Y. Iwamoto, M. Yotsuyanagi, M. Sugimoto NEC Corp., Kanagawa, Japan

A 3.3V 6.2x6.2mm2 single-chip 16CAP transceiver for ATM-LAN using 0.35um BiCMOS technology includes 8b A/D converter, clock recovery circuit, transmitter, and digital modulation/demodulation. The supply voltage is 3.3V and power consumption is 1.1W.

15.3 - A 1.25Gb/s 460mW CMOS Transceiver for Serial Data Communication - 2:30 PM

D-L. Chen, M. Baker Symbios Logic, Fort Collins, CO

A 12mm2 1.25Gb/s CMOS device with both transmitter and receiver on a single chip has three phase-locked loops for clock generation and recovery, a serializer, a deserializer, and word alignment logic. It is in a 0.5um single-poly, triple-metal digital CMOS process and dissipates 460mW.

BREAK 3:00 PM

15.4 - 3.3V, 50Mb/s CMOS Transceiver for Optical Burst-Mode Communication - 3:15 PM

N. Ishihara, M. Nakamura, Y. Akazawa, N. Uchida1, Y. Akahori1 NTT System Electronics Labs, Kanagawa, Japan 1NTT Opto-electronics Labs, Kanagawa, Japan

A 3.3V, 50Mb/s transceiver for optical burst communication in 0.8um CMOS implements an adjustment-free instantaneous response receiver with -35dBm to -11.4dBm input optical receive range, and a laser diode driver. The chip dissipates 0.3W and has a 5x5mm2 die

15.5 - A 2.488Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection - 3:45 PM

R. Walker, C. Stout, C-S. Yen Hewlett-Packard Labs., Palo Alto, CA

Adjustment-free clock and data recovery for 2.488Gb/s SONET is provided by a 1.77W, 3.45x3.45mm2 chip in 25GHz fT silicon bipolar. The chip uses an on-chip VCO for low-cost packaging, operates from 2-3Gb/s over process, voltage and temperature, and requiries one off-chip filter capacitor. For network monitoring, a loss-of-signal detector has trigger threshold programmable between 10E-4 and 10E-6 BER.

15.6 - A 4.25GHz BiCMOS Clock-Recovery Circuit with an AV-DSPD Architecture for NRZ Data Stream - 4:15 PM

S. Nakamura, A. Tajima, Y. Kinoshita, Y. Suemura, M. Fukaishi, H. Suzuki, T. Itani, H. Miyamoto, N. Henmi, T. Yamazaki, M. Yotsuyanagi NEC Corp., Kanagawa, Japan

Using the absolute value of divided signal phase difference to control the VCO, clock recovery at a frequency twice that of the internal phase detector is accomplished. It is fabricated in 0.25um BICMOS and consumes 150mW from 3.3V.

15.7 - A 500Mb/s, 20-Channel CMOS Laser Diode Array Driver for a Parallel Optical Bus - 4:45 PM

P. Xiao, D. Kuchta, K. Stawiasz, H. Ainspan, J-H. Choi1, H. Shin IBM, T. J. Watson Research Ctr., Yorktown Heights, NY 1Seoul City University, Seoul, Korea

A 20-channel, 500Mb/s/channel CMOS laser diode (LD) driver for a parallel optical interconnect has an LVDS input interface with acceptable common-mode from 50mV to 2.35V. It supports four different modes of operation with maximum data throughput at 10Gb/s. The channel data skew is below 100ps. It uses a standard 3.3V power supply with 1.6W of power dissipation.

CONCLUSION 5:15 PM

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