Intelligent DRAMs (IRAMs) combine processors and DRAM to provide high bandwidth for predictable access (e.g. matrix multiplication) and low latency for unpredictable access (e.g. data base). Applications graphics, vector processing, portable and embedded products. A vector processor in a 0.18um process would offer 8GFLOPS and 100GB/s.
Current high-bandwidth DRAM data rates of 600Mb/s/pin combined with expected 30% jitter reduction in a new design and process with a 32b-wide device would result in a 5.2GB/s datapath from a single 64Mb DRAM with an estimated 2.5W power dissipation. This increases the fill rate over current SDRAMs by 19.7x.
The proposed parallel processing RAM (PPRAM) integrates four processing elements, each consisting of a 32b RISC processor, an 8MB DRAM and a 24kB cache SRAM on an approximately 450mm2 die in a 0.25um CMOS mixed-DRAM-and-logic process. Multiple processors exhibit higher-level parallelism and the integrated bus relieves the memory bottleneck problem.
The autonomous reconfigurable cell array (ARCA) uses the redundancy, regularity and programmability of reconfigurable logic circuits to repair logic by self-detecting faults in real-time and recovering while remaining on-line. An 8x8-cell array occupies 1.9x1.6mm2 in 0.35um CMOS.
Stochastic dopant fluctuations cause 45-89% threshold deviations in a 0.10um process. The variations in threshold, saturation current and sub-threshold conduction require new circuit and system design methodologies. Similarily, stochastic wire length distributions described by Rent s rule aid interconnect design and power dissipation estimation.
A GaAs 100k-gate array has digital variable-delay macro cell for measurement instruments and eliminates of clock skew. Using a meshed air bridge structure, a rise edge selector, and a delay circuit with a discharge control path, the macro cell produces 24.4ns span and 12ps resolution with 250mW/cell dissipation.
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