SESSION FP13

SALON 7

OVERSAMPLING DATA CONVERTERS

Chair: B-S. Song, University of Illinois, Urbana, IL
Associate Chair: D. Kerth, Crystal Semiconductor, Austin, TX

13.1 - A 16b SIGMA DELTA Pipeline ADC with 2.5MHz Output Data Rate - 1:30 PM

T. Brooks, D. Robertson, D. Kelly, A. Del Muro, S. Harston Analog Devices, Wilmington, MA

A 0.6um CMOS ADC sampling at 20MHz combines SIGMA DELTA and pipeline techniques to provide 90dB dynamic range at an 8x oversampling ratio. The 5.7x6.2mm chip exhibits 89dB SNR over a 1.25MHz input bandwidth and consumes 550mW at 5V.

13.2 - Low-Voltage Double-Sampled SIGMA DELTA Converters - 2:00 PM

D. Senderowicz1, G. Nicollini, P. Confalonieri, S. Pernici, A. Nagari, C. Dallavalle SGS-Thomson Microelectronics, Agrate Brianza, Italy 1SynchroDesign, Inc., Berkeley, CA

Double-sampling 2nd-order SIGMA DELTA ADC and DAC clocked at 1MHz exhibit dynamic ranges of 88 and 84dB within 3.4kHz bandwidth and consume 0.55 and 0.6mW respectively at 1.5V using 0.5um CMOS. Capacitor mismatch. typically appearing as noise in double sampling, is translated to common-mode voltage in this ADC.

13.3 - A Two-Path Bandpass SIGMA DELTA Modulator for Digital IF Extraction at 20MHz - 2:30 PM

A. Ong, B. Wooley Stanford University, Stanford, CA

A bandpass SIGMA DELTA modulator with two paths time-interleaved at 40MHz digitizes a 200kHz bandwidth signal centered at 20MHz with 75dB dynamic range. The mirror image of the signal is suppressed by 42dB. The 0.6um CMOS chip dissipates 72mW at 3.3V.

BREAK 3:00 PM

13.4 - A Bandpass SIGMA DELTA Modulator with 85dB SNR and Center Frequency Continuously Programmable from 0 to 70MHz - 3:15 PM

G. Raghavan, J. Jensen, R. Walden, W. Posey1 Hughes Research Labs, Malibu, CA 1Hughes Radar and Communication Systems, El Segundo, CA

A continuous-time, 2nd-order bandpass SIGMA DELTA modulator with tunable center frequency range from 0 to 70MHz exhibits an SNR ranging from 85dB for a 370kHz bandwidth to 42dB for a 62.6MHz bandwidth. The InP HBT chip consumes 1.4W and occupies 0.75x0.75mm .

13.5 - A Quadrature Bandpass SIGMA DELTA Modulator for Digital Radio - 3:45 PM

S. Jantzi, K. Martin, A. Sedra University of Toronto, Ontario, Canada

A 4th-order complex SIGMA DELTA modulator clocked at 10MHz digitizes narrow-band 3.75MHz I and Q inputs with SNR of 62dB for 200kHz bandwidth inputs. SNR increases to 67dB for 100kHz and to 72dB for 30kHz inputs. The chip consumes 130mW at 5V and occupies 2.4x1.8mm in 0.8um CMOS.

13.6 - A 5V, 118dB DELTA SIGMA Analog-to-Digital Converter for Wideband Digital Audio - 4:15 PM

K. Leung, E. Swanson, K. Leung, S. Zhu Crystal Semiconductor Corp., Austin, TX

A stereo, leap-frog switched-capacitor, DELTA SIGMA converter achieves 118dB and 115dB dynamic ranges (unweighted) over 22kHz and 44kHz bandwidths, respectively. Twin seventh-order modulators sample at 6.144MHz and use calibrated tri-level quantizers. The 30mm2, 0.8um CMOS device consumes 760mW at 5V.

13.7 - A 2.3mW CMOS SIGMA DELTA Modulator for Audio Applications - 4:45 PM

E. van der Zwan Philips Research Labs., Eindhoven, The Netherlands

A 4th-order 128x oversampling SIGMA DELTA modulator with continuous-time loop filter exhibits 96dB dynamic range over a 20kHz bandwidth and 104dB THD at 1kHz. The chip consumes 2.3mW at 3.3V. Another implementation shows 101dB dynamic range and -110dB THD with 6.6mW.

CONCLUSION 5:00 PM

Go back to Table of Contents