DISCUSSION SESSIONS
FE8 - DRAM + Logic Integration:
Which Architecture and Fabrication Process
-- (Salon 11 - 15)
Moderator: Osamu Kimura, NEC, Sagamihara, Japan
Co-moderator: Richard Crisp, Rambus, Mountain View, CA
Organizer: Michihiro Yamada, Mitsubishi, Itami, Hyogo, Japan
This panel seeks to satisfy both system makers and LSI vendors by integrating DRAM +
logic on one chip. Applications suitable to DRAM +Logic integration are discussed.
How can wafer process and circuit technologies satisfy cost/performance requirements?
Test strategy and design methodology are included. To what extent and how soon will
DRAM + Logic integration be required, and how is it to be achieved? Which
architecture and wafer process is the preferable basis, DRAM or logic?
Panel:
Michael Nagy, SGI, Mountain View, CA
Henry Lie, Hewlett Packard, Palo Alto, CA
Roelof Salters, Philips, Eindhoven, the Netherlands
Kenji Numata, Toshiba, Kawasaki, Japan
Takao Watanabe, Hitachi, Tokoyo, Japan
Kazunori Saitoh, Mitsubishi, Itami, Hyogo, Japan
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