Management of power dissipation and clock distribution are two examples of the many challenges faced by designers of complex digital CMOS circuits. Such issues generate an evolving debate between advocates of asynchronous design and champions of synchronous design. It is not clear how this debate will end, as many aspects of the design also play important roles: application, costs, testability, EMC, and robustness. Panel members representing the two camps will exchange views mutually and with the audience.
Go back to Table of Contents