SESSION FA8

SALON 7

DATA CONVERTERS

Chair: H-S. Lee, MIT, Cambridge, MA
Associate Chair: J. Fattaruso, Texas Instruments, Dallas, TX

8.1 - A MOSFET-Only, 10b, 200kSample/s A/D Converter Capable of 12b Untrimmed Linearity - 8:30 AM

C. Hammerschmied, Q. Huang Swiss Federal Institute of Technology (ETH), Zurich, Switzerland

A successive-approximation ADC is based on a current-division ladder. Most chips show THD of -70dB or better without trimming or self-calibration. The ADC in standard single-poly 1um CMOS requires 5.2mm2, and consumes 12mW at 5V.

8.2 - A 12b 50MSample/s Cascaded Folding and Interpolating ADC - 9:00 AM

P. Vorenkamp, R. Roovers1 Philips Composants et Semiconducteurs, Caen Cedex, France 1Philips Research Laboratories, Eindhoven, The Netherlands

An ADC features an integrated track-and-hold circuit that enables SNR>64dB and SFDR >70dB, measured over 70MHz signal bandwidth. The 7mm2 ADC is in a 13GHz, 1um BiCMOS process and dissipates 300mW from 5.0V.

8.3 - An Embedded 170mW 10b 50MSample/s CMOS ADC in 1mm2 - 9:30 AM

K. Bult1, A. Buchwald, J. Laskowski Broadcom Corp., Irvine, CA 1UCLA, Los Angeles, CA

A distributed-gain preamplifier uses averaging to improve resolution by 4b in DNL, and 2b in INL in a flash 10b ADC. In 0.5um, triple-metal, single-poly CMOS, the circuit is 1.4x1.4mm2 including a bandgap and a S&H. The untrimmed ADC dissipates 240mW and exhibits 54dB SNDR with a 12MHz 90% full-scale input.

BREAK 10:00 AM

8.4 - A 12b 128MSample/s ADC with 0.05LSB DNL - 10:15 AM

R. Jewett, K. Poulton, K-C. Hsieh, J. Doernberg Hewlett-Packard Laboratories, Palo Alto, CA

A two-step flash ADC with dynamic element matching and dither achieves 0.05LSB differential nonlinearity and 61.5dB SNR. Harmonics are <-72dBc for signals up to 55MHz. 14,000 npns in a 25GHz fT bipolar process dissipate 5.7W. On-chip digital integrators adjust critical gains.

8.5 - A 2.7V 300MHz Track-and-Hold Amplifier - 10:45 AM

A. Karanicolas Morganville, NJ

A fully-differential bipolar track-and-hold amplifier employs open-loop linearization. THD is less than -65dB for a 300MHz clock and a full-scale 50MHz input. The THA consumes 30mW from a 2.7V supply and is fabricated in 0.5um, 18GHz BiCMOS.

8.6 - A 1GSample/s 10b Full Nyquist Silicon Bipolar Track&Hold IC - 11:15 AM

T. Baumheinrich, B. Pr gardier1, U. Langmann Ruhr-Universit t Bochum, Bochum, Germany 1Now with Rockwell Semiconductor Systems, Newport Beach, CA

A track-and-hold IC achieves THD of less than -62dB, corresponding to 10b, over the Nyquist band at 1GSample/s. The chip in 25GHz fT, 0.4um-emitter silicon bipolar technology consumes 490mW from 5.2V.

8.7 - A 10b 250MHz BiCMOS Track-and-Hold - 11:45 AM

U. Gatti, C. Fiocchi, F. Maloberti1 Italtel, Milano, Italy 1University of Pavia, Pavia, Italy

A 0.8um 126GHz T BiCMOS track and hold circuit achieves -61.6dB THD with a 70MHz, 1Vpp sinewave at 250MSample/s. Hold-mode feedthrough is -57dB and pedestal error is 1mV. The chip dissipates 225mW from 5V.

8.8 - A 15b 5MSample/s Low-Spurious CMOS ADC - 12:00 noon

S-U. Kwak, B-S. Song, K. Bacrania1 University of Illinois, Urbana, IL 1Harris Semiconductor, Melbourne, FL

A 4-stage pipeline ADC incorporates self-calibration to achieve 0.75LSB DNL and 1.77LSB INL. All harmonics are <-93dB. The chip in 1.4um CMOS occupies 4.4x6.2mm2 active area and consumes 60mW using 5V.

CONCLUSION 12:30 PM

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