Field-effect transistors incorporating a strained Si/SiGe layer for high mobility channels are presented. A 0.4um enhancement-mode n MODFET ring oscillator yields 25ps gate delays at 0.8V drain bias for a 10x reduction in power-delay product compared to circuits in bulk Si.
As the demand for bandwidth increases, wireless transceivers will become more complex. CMOS is well suited to implement the low noise, wide dynamic range and high levels of integration required in the analog RF, IF and digital backends of modern transceivers.
A 1Gb/s 8-channel array OEIC operates with 3.3V supply voltage. Receiver sensitivity is 10.4dBm at 1Gb/s data rate with a photo-detector quantum efficiency of 20% at a 0.98um wavelength. The 3x8mm2 chip dissipates 94mW/channel.
A 2:1 static frequency divider in a 68GHz/0.5um double-polysilicon self-aligned Si/SiGe heterojunction bipolar technology operates up to 42GHz. The core divider circuit dissipates 300mW from a -6.5V supply, and total chip area is 0.55x0.55mm2.
A 4b flash ADC in SiGe HBT technology (fT/fmax=45/60GHz) with pipelined encoding is fully functional at 8GSample/s. Maximum input bandwidth is 4GHz, based on beat-frequency measurements. Both DNL and INL are <0.25LSB. The chip has >1k transistors and consumes 500mW at 3.6V.
New heterostructure configurations using GaAs/AlGaAs technology to produce two-dimensional CCD matrices with 10k storage elements per um2. The potential of three-dimensional structures using field emission incorporating resonant tunneling for multivalued logic is discussed.
Vector processing with 20Gb/s asynchronous superconducting quantum digital circuits using niobium-based Josephson-junction technology is described. Experimental results of key components are presented, including a 20Gb/s register and 38GHz clock generator.
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