A -inch progressive scan CMOS image sensor with 640(H)x480(V) pixels is fabricated in a 0.6um CMOS process. Several pixel structures are described. The sensor with 5.6x5.6um2 pixel operates with 5.0V single 5V supply and <30mW power consumption.
A 400,000 pixel current-mode CMOS image sensor with electronic pan, zoom, and shutter operates with 3.5V or 5V supplies. The pixel includes only three FETs, one bias bus, and two signal inputs. A current-reset mode and difference mode compensate for component mismatch. Dynamic range >1000:1 is demonstrated at 2Frames/s continuous operation.
A 128x128 pixel image sensor is integrated with an analog 2-D discrete cosine transform (DCT) processor and a variable quantization-level ADC using 0.35um CMOS. Two analog 2-D DCT cores can perform real-time (30Frame/s) encoding of CIF-format (288x352) image with 10.8mW at 3V in a complementary fashion.
A 4M pixel charge-modulation device image sensor has three readout modes: full, arbitrary block, and skip access. Block and skip modes provide partial and whole image in real time, respectively. The sensor uses 100mW at 12MHz horizontal clock frequency.
A 2/3-inch 1.3M pixel progressive scan CCD for still/video cameras with 49MHz horizontal CCD operation and a 140MHz bandwidth amplifier achieves 30Frame/s. 8-phase drive for vertical CCDs also enables 1049 line wide dynamic range interlaced scan. A narrow channel barrier overflow drain is attached for draining needless charge.
A real-time analog image encoder chip receives analog image data signals from a B/W image sensor and compresses them to an average 0.2b/pixel using a subband scheme based on vector quantization. The chip, in 0.8um CMOS, encodes 288(H)x192(V) pixel images at 60Frames/s. The chip consumes 16mW at 3V.
A 1Vp-p video signal is sampled and amplified to a 3Vp-p liquid crystal control signal to reduce power consumption (19.8mW, 3.3 V) and to weaken electromagnetic radiation from the input lines of the driver ICs. The 342 outputs have a standard deviation of 2.5mV accomplished by a suppression of 1/sqrt(9), in the sample-and-hold stage and the gain stage by shuffling over 9 function units.