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Six tutorials run in two parallel sessions on Wednesday, February 7 and are followed by a social hour. Tutorials introduce specialized circuit areas that are focus of ISSCC96. The objective is understanding and perspective of work presented at ISSCC96. Each tutorial is linked to specific ISSCC96 Paper Sessions: overview of system applications, historical perspective of chip architectures and circuit approaches, understanding of the state of the art, and feel for future directions. Tutorials are held in Golden Gate Hall.
Tutorial 1: Monolithic Phase-Locked Loops (1:00-2:30)
Instructor: Behzad Razavi, AT&T Bell Labs, Holmdel, NJ
Why phase-lock? Basic concepts, operating principles and limitations of a simple PLL; loop dynamics; design of building blocks (VCOs, phase/frequency detectors, charge pumps) in CMOS and bipolar technologies; noise in PLLs; applications in wireless and digital systems.
Tutorial 2: Techniques for Low-Power Digital Signal Processing
Instructor: Anantha P. Chandrakasan, MIT, Cambridge, MA
Circuits and architectures. Voltage reduction techniques: concurrency-based architecture scaling and device optimization. Efficient dc-dc conversion for low-voltage operation. Reduced-swing logic and adiabatic charging lower energy at a fixed supply. Minimizing switched capacitance: operation reduction, optimizing data representation and signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, and optimizing arithmetic structures and circuits.
Tutorial 3: Micromachined Sensors
Instructors: Dennis L. Polla, Univ. of Minnesota, Minneapolis, MN
Gregory T. A. Kovacs, Stanford University, Stanford, CA
Advances in micromachining, thin-film materials, and IC process integration open opportunities in a variety of fields. Common transduction mechanisms realized on a semiconductor chip: mechanical, optical, magnetic, thermal, chemical, and biological sensing. Overview of micromachining technologies. Discussion of sensing, actuation and systems integration.
Tutorial 4: Dynamic Logic: Clocked and Asynchronous
Instructor: Ted Williams, Silicon Graphics, Mountain View, CA
Characteristics and performance of precharge, postcharge, self-resetting, single-edge, and domino chain dynamic logic. Where to use and interface these techniques. Choices for clocked and dual-rail self-clocked latches, how latches follow or combine with dynamic logic, and how to control when dynamic portions reset in clocked and self-timed pipelines. Charge-sharing, noise margin, power use, latency, throughput, and area trade-offs.
Tutorial 5: RF ICs for Cellular and Cordless Telephones
Instructor: Paul Davis, AT&T Bell Labs, Reading, PA
0.8-2.0GHz RF IC subcircuits (amplifiers, mixers, phase shifters, and oscillators) in context of selected cellular and cordless radio system requirements. Transmitter, receiver, and synthesizer architectures and subcircuits addresses requirements such as RF sensitivity, interference rejection, and spurious signals. Emphasis is on RF bipolar analog ICs.
Tutorial 6: Nonvolatile Memory Design
Instructor: Jagdish Pathak, Sub Micron Circuits, Los Altos Hills, CA
Memory cells, layout, and architecture. Evolution of nonvolatile memories from ROM to Flash. Cell operation and disturbs for different architectures. High- and low-voltage circuits and isolation, high-speed design in arrays, and designing around these limitations. High-voltage generation and charge-pump design. Definition and purpose of test modes for in-house testing.
Registration:
Use ISSCC96 Registration Form on Advance Program centerfold
Behzad Razavi received the BSEE from Tehran (Sharif) University of Technology in 1985 and MSEE and PhDEE from Stanford in 1988 and 1991, respectively. Since 1992, he has been with AT&T Bell Laboratories, Holmdel, NJ, where his research involves IC design for communications and wireless systems. He is author of two books published by IEEE Press.
Anantha P. Chandrakasan received the PhD in EECS from U.C.Berkeley in 1994. Since September 1994, he has been the Analog Devices Career Development Assistant Professor of EE at MIT. His research interests include the ultra-low-power implementation of digital signal processors, low-voltage circuit design, wireless system design, and CAD tools. He is a coauthor of book on low-power CMOS design.
Dennis L. Polla attended MIT and received four degrees in electrical engineering and physics. He received the PhD in Electrical Engineering and MBA from the University of California, Berkeley. He has held faculty teaching positions at UC Berkeley, Yale University, and the University of Minnesota ,where he is currently Professor of Electrical Engineering and Director of the Microtechnology Laboratory. He is a former Presidential Young Investigator and is a member of several Department of Defense advisory groups.
Gregory T. A. Kovacs holds BASc EE from University of British Columbia, MS in Bioengineering from the University of California, Berkeley, the PhD EE and MD from Stanford. In 1991, he joined Stanford where he teaches courses in electronic circuits, micromachined transducers and biomedical engineering. He held the Robert N. Noyce Family Faculty Scholar Chair, received an NSF Young Investigator Award and is Terman Fellow. His research is in solid-state sensors and actuators, micromachining, neural/electronic interfaces, integrated circuit fabrication, medical instruments, and biotechnology.
Ted Williams holds BS from Caltech, and MS and PhD from Stanford. He was at Xerox and HP Labs, and was VP of IC Development at Silicon Engines. From 1990 to 1995, he was VLSI Chief Engineer at HaL, for custom circuits and CAD tools. He is now with the MTI division of Silicon Graphics. He has designed precharged and self-timed circuits in products, and has lectured at technical institutes in Denmark and Norway and at Stanford, and is on program committees for conferences on circuits and computer arithmetic.
Paul Davis received BSEE from West Virginia University in 1959, MSEE from MIT in 1961, and PhD from Lehigh in 1968. At Bell Labs Reading PA since 1962, he has done silicon device modeling and analog and mixed-signal IC designs for telephones, central offices, and fiber-optic systems. Since 1988 he has defined and designed RF ICs for digital cellular and cordless phones. He is coauthor of six ISSCC papers and holds nine US patents.
Jagdish Pathak received BEEE and MEEE from University of Indore, India in 1967 and 1969, respectively, and diploma in business management from Deli University in 1970. He taught electronics in India, and joined Fairchild in 1976, working on DRAM design. He also has designed memory and PLD devices at Intel, Cypress and Alliance. He is now president of Sub Micron Circuits. He has published and holds patents, having worked on DRAM, SRAM, EPROM, EEPROM Flash and PLD products.
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