Go back to the ISSCC page
HIGH-SPEED, LOW-POWER
Chair: J. Cressler, Auburn University, Auburn, AL
Associate Chair: J. van der Spiegel, University of
Pennsylvania, Philadelphia, PA
5.1 TCAD for Analog-Circuit Applications: Virtual Device and Instruments (1:30)
R. Dutton, B. Troyanovsky, Z. Yu, E.C. Kan, T. Chen
Stanford University, Stanford, CA
Technology-computer-aided-design (TCAD) supports analog circuit design such as predictive SPICE-model extraction, improved analog-device models, parasitics, noise, and reliability analysis. TCAD allows the creation of virtual wafers and devices. A virtual spectrum analyzer extracts important analog parameters such as intermodulation distortion and cross-talk.
5.2 Si/SiGe HBT Technology for Low-Cost Monolithic Microwave Integrated Circuits (2:00)
L. Larson, M. Case, S. Rosenbaum, D. Rensch, M. Chen, P. MacDonald, M. Matloubian, D. Harame(1), J. Malinowski(1), B. Meyerson(1), M. Gilbert(1), S. Maas(2)
Hughes Research Labs, Malibu, CA
(1)IBM Microelectronics Div., East Fishkill, NY
(2)Non-Linear Technology, Long Beach, CA
SiGe HBT monolithic microwave IC technology delivers voltage-controlled oscillators with 80mW output power at 12GHz, phase noise <80dBc/Hz at 100kHz, and tuning range of 500MHz. Mixers yield 2dB conversion gain from 9-11GHz with >30dB LO-RF isolation. Single-stage power amplifiers provide 80mW output and 6dB small-signal gain at 9GHz.
5.3 RF Analog and Digital Circuits in SiGe Technology (2:30)
J. Long, M. Copeland , S. Kovacic(1), D. Malhi(1), D.L. Harame(2)
Carleton University, Ottawa, Canada
(1)Bell-Northern Research, Ltd., Ottawa, Canada
(2)IBM Microelectronics Div., East Fishkill, NY
A SiGe HBT 2.3-5.9GHz frequency-halver with quadrature-phase outputs operates at 220uA on 1.9V. A preamplifier of a 2.4GHz wireless downconverter has 0.95dB noise figure with 10.5dB gain. A negative- feedback amplifier has 8dB gain with 16.9GHz 3dB bandwidth. An ECL clock generator and retiming circuit operates at 10Gb/s with <10-9 BER.
BREAK (3:00)
5.4 A 0.5V SIMOX-MTCMOS Circuit with a 200ps Logic Gate (3:15)
T. Douseki, S. Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, T. Tsuchiya
NTT LSI Labs, Kanagawa, Japan
A SIMOX multi-threshold CMOS circuit combines fully-depleted low-Vth CMOS logic gates and body-connected variable high-Vth MOSFETs with 0.4V power supply. The 2-NAND gate of a gate-chain test element group (TEG) in a 0.25um technology has a delay time of 80ps at 1V and 197ps at 0.5V. A 0.5V, 40MHz, 0.35mW, 16b ALU consumes less than 5nW in the sleep mode.
5.5 0.25um CMOS/SIMOX Gate Array LSI (3:45)
M. Ino, H. Sawada, K. Nishimura, M. Urano, H. Suto, S. Date, T. Ishihara, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, Y. Arita, K. Izumi, K. Takeya, T. Sakai
NTT LSI Labs, Atsugi, Japan
A 0.25um CMOS/SIMOX 300k-gate (3M-transistor) gate-array LSI uses fully-depleted MOSFETs on a low-dose SIMOX substrate. The speed of a 120k-gate test LSI at 2V is 25% higher than that of a bulk/CMOS gate-array.
5.6 A Ultra-Low-Voltage SOI CMOS Path-Gate Logic with a Body-Bias-Controlled Buffer (4:15)
T. Fuse, Y. Oowaki, S. Watanabe, K. Ohuchi, J. Matsunaga
Toshiba Corp., Kawasaki, Japan
SOI CMOS path-gate logic is composed of gate-body connected SOI path-gates and a buffer with the body-bias controlled by the complementary double-rail input. A full-adder is about 10 times faster than the conventional SOI complementary path-gate logic at 0.5V. A 16x16 bit multiplier has 70pJ power-delay product (including 50pF I/O), an order of magnitude improvement over conventional CPL.
CONCLUSION (4:45)
SOCIAL HOUR (5:00)
Go back to the SSCS page
If you have any comments for the ISSCC, please forward them to
Comments related to the maintenance of this web site should be sent to sscs@eecg.toronto.edu .