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Chair: R.. Yamasaki, Silicon Systems Inc., Tustin, CA
Associate Chair: M. Rhodes, Pacific Communications Sciences Inc., San Diego, CA
4.1. A 150Mb/s PRML Chip for Magnetic Disk Drives (1:30)
S. Mita, Y. Ouchi, T. Takashi, N. Sato, H. Aoi, S. Minosima, T. Hirai H. Miyasaka, R. Shimokawa, T. Matsuura, H. Sawaguchi, S. Miyazawa, K. Hikasa
Hitachi Ltd., Odawara, Japan
(1+D) equalization and switched 1st to 2nd order PLL loop are used to improve the performance of a digital PRML channel chip. The 47mm2 0.7um BiCMOS chip dissipates 1.45W at 150Mb/s.
4.2. A 130Mb/s PRML Read/Write Channel with Digital Servo Detection (2:00)
T. Tuttle, D. Vishahadatta, M. Goldenberg, D. Kuai, I. Mehr, A Singh, R. Trujillo, D. Welland, R. Gomez, F. Aram, J.Hein , D. Reed(1), J. Mitchem(1), W. Bliss(1), A. Armstrong(1), R. Behrens(1), T. Dudley(1), C. Duey(1), J. Meadows(1), W. Forland(1),R. Hull(2), D. Turner(2)
Crystal Semiconductor Corp., Austin, TX
(1)Cirrus Logic, Broomfield, CO
(2)Western Digital Corp, Irvine, CA.
A data-recovery IC for hard-disk drives implements both data and embedded servo detection in the digital domain. The 28mm2 0.6um CMOS chip contains 31k analog transistors and 26k digital gates, requires no external components other than standard decoupling capacitors, and dissipates 1.35W at 133Mb/s.
4.3. A 200Mb/s PRML Read/Write Channel IC (2:30)
K. Parsi, N. Rao, R. Burns, A. Chaiken, M. Chambers, R. Cheung, B. Forni, D. Harnishfeger, C. Jam. S. Kaylor, M. Pennell, J. Perez, M. Rohrbaugh, M. Ross, G. Stuhlmiller, N. Weiner.
Motorola Inc., Tempe, AZ.
PR4 equalization is achieved via a continuous-time filter and a 7-tap adaptive continuous-time transversal equalizer using sign-sign least-mean-square adaptation. The 20mm2, 0.5um BiCMOS chip with an analog Viterbi detector dissipates 0.8W at 200Mb/s.
BREAK (3:00)
4.4. A 160MHz Front-End IC for EPR-IV PRML Magnetic-Storage Read Channels (3:15)
P. Pai, A. Brewster, A. Abidi
UCLA, Los Angeles, CA
An IC uses a 6-pole, 2-zero continuous-time filter architecture to achieve better performance than the conventional read-channel 7-pole, 2-zero plus 7-tap FIR equalization. An analog EPR-IV timing-recovery PLL is included and the chip is fabricated in 1um CMOS.
4.5. A CMOS 6b 200MSample/s 3V Supply A/D Converter for a PRML Read-Channel LSI (3:45)
S. Tsukamoto , I. Dedic(1), T. Endo, K. Kituta, K. Goto(2),O.Kobayashi(2).
Fujitsu VLSI Ltd., Kasugi, Japan
(1)Fujitsu Microelectronics Ltd., Maidenhead, UK
(2)Fujitsu, Kawasaki, Japan
A 0.5um CMOS 6b ADC with 3V supply for a PRML read channel LSI achieves a conversion rate of 200MSample/s using an interleaved auto-zeroing architecture and output-swing-limiting comparator.
4.6. A 200Mb/s Analog DFE Read Channel (4:15)
N. Sands, M. Hauser, R. Dakshinamurthy
Philips Semiconductors, Sunnyvale, CA.
A read-signal processor incorporates adaptive forward and decision feedback equalization with extensive use of analog signal processing. Nonlinear feedback processing is used to mitigate nonlinear intersymbol interference. The 52mm2 0.8um BiCMOS chip dissipates about 0.7W at 200Mb/s.
4.7. A 200MHz 9-Tap Analog Equalizer for Magnetic-Disk Read Channels in 0.6mm CMOS (4:30)
D. Xu, Y. Song, G. Uehara.
University of Hawaii, Honolulu, Hawaii
An analog transversal-filter architecture using switched-capacitor technique implements a 9-tap programmable equalizer suitable for PRML read-channel applications. The prototype equalizer has an output sampling rate of 200MHz and is in 0.6um CMOS technology.
CONCLUSION (4:45)
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