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Chair: A. Baker, Intel Corp., Folsom, CA
Associate Chair: Y-H. Jun, LG Semicon, Seoul, Korea
2.1 A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass-Storage Applications (1:30)
T-S. Jung, Y-J. Choi, K-D. Suh, B-H. Suh, J-K. Kim, Y-H. Lim, Y-N. Koh, J-W. Park, K-J. Lee, J-H. Park, K-T. Park, J-R. Kim, J-H. Lee, H-K. Lim
Samsung Electronics Co., Kiheung, Korea
A NAND flash memory stores two bits per cell by controlling the program-threshold-distribution width to 0.4V with a 0.8V gap between states. Use of a 1-metal, 2-poly 0.4um CMOS process results in a 117mm2 die. 12.9 MB/s read and 0.5MB/s write are achieved.
2.2 A 140mm2 64Mb AND Flash Memory in a 0.4mm Technology (2:00)
H. Miwa, T. Tanaka, K. Oshima, Y. Nakamura, T. Ishii, A. Ohba(1), Y. Kouro(1), T. Furukawa, Y. Ikeda, O. Tsuchiya, R. Hori, K. Miyazawa
Hitachi Ltd. , Tokyo, Japan
(1)Mitsubishi Electric Corporation, Tokyo, Japan
A 64Mb flash memory for 3.3V memory card use has 512B program and erase sector. Source-line plate layout, command-address input multiplexing , serial address comparison for redundancy and a 1.36um2 cell result in 67% array efficiency.
2.3 A 98mm2 3.3V 64Mb Flash Memory with FN-NOR Type 4-Level Cell (2:30)
M. Ohkawa, H. Sugawara, N. Sudo, M. Tsukiji, K. Nakagawa, M. Kawata, K. Oyama, T. Takeshima, S. Ohya
NEC Corporation, Sagamihara, Japan
A 64Mb flash memory uses 2 bits per cell and drain-voltage-controlled writing. 6.3us-per-byte program speed is achieved by writing 128 cells at a time. 16 cells in 1.52x15.52um2 results in a 98mm2 die.
BREAK (3:00)
2.4 Bit-Line-Clamped Sensing Multiplex and Accurate High-Voltage Generator for Quarter-Micrometer Flash Memories (3:15)
T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto,
T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, K. Kimura
Hitachi Ltd., Tokyo, Japan
A 128Mb 2.5V flash memory in 0.25um phase- I-line technology occupies 106mm2 using a 0.4um2 cell. Bipolar devices inherent in this triple-well technology result in 1% reference-voltage variation at 5mA.
2.5 A 1Mb 2-Transistor/bit Non-Volatile Content-Addressable Memory Based on Flash Memory Technologies (3:45)
T. Miwa, H. Yamada, Y. Hirota, T. Satoh, H. Hara
NEC Corporation, Sagamahara, Japan
A 1Mb content-addressable memory based on flash-memory technology with a pair of flash-memory cells per bit is more efficient than designs using SRAM or DRAM. The cell is 10.34um2 and die is 42.9mm2 in 0.8um CMOS. The flash CAM can be searched for masked binary data. Read and search access times are 130ns and 140ns respectively with 5V supply.
2.6 A 3.3V-only 16Mb Flash Memory with a new Row-Decoding Scheme (4:15) S. Atsumi, M. Kuriyama, A. Umezawa, H. Banba, N. Ohtsuka, N. Tomita, Y. Iyama, T. Miyaba, R. Sudoh, S. Mori, E. Sakagami, Y. Yamaguchi, N. Arai, M. Tanimoto, Y. Hiura, E. Kamiya
Toshiba Corp., Kawasaki, Japan
A 30ns 16Mb flash memory in 0.4mm double-well CMOS uses negative gate bias erase for 3.3V operation. A double word-line with second aluminum and quasi-differential sensing achieve fast random access. Row redundancy with self-convergence improves yield.
2.7 A 55ns 0.35mm 5V-only 16Mb Flash Memory with Deep Power Down (4:45)
B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, J. Yu, M. Van Buskirk, S. Kawamura(1), K. Kurihara(1)
Advanced Micro Devices, Sunnyvale, CA
(1)Fujitsu Ltd., Kawasaki, Japan
This 16Mb flash memory in 0.35um triple-well CMOS with a 1.21um2 single-transistor cell occupies a 48mm2 die. On-chip regulated charge pumps generate voltages for channel hot-electron programming and negative-gate-source erase. A CEB pin brings the chip to 1uA deep power down and resumes normal access without latency.
CONCLUSION (5:00)
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