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Chair: T. Furuyama, Toshiba, Essex Junction, VT
Associate Chair: B. Keeth, Micron Technology, Boise, ID
23.1 A 60ns 1Mb NV Fe Memory with Non-Driven Cell Plate Line Write/Read Scheme (1:00)
H. Koike, T. Otsuki, T. Kimura, M. Fukuma, Y. Hayashi, Y. Maejima, K. Amanuma, N. Tanabe, T. Matsuki, S. Saito, T. Takeuchi, S. Kobayashi, T. Kunio, T. Hase, Y. Miyasaka, N. Shohata, M. Takada
NEC Corp., Sagamihara, Japan
A 3.3V non-driven cell plate line write/read memory uses a 34.7um2 SBT (SrBi2Ta2O9) 1-transistor 1-capacitor cell. A 1.0um single-level-Al CMOS process yields a 90.9mm2 chip with 60ns access and 100ns cycle times.
23.2 A 1MB 100MHz Integrated L2 Cache Memory with 128b Interface and ECC Protection (1:30)
G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni,
C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh,
M. Vincent, T. von Reyn, J. Zimmerman
IBM Microelectronics Division, Essex Junction, VT
A hierarchical integrated L2-cache chip combines a fully-associative 3ns SRAM line buffer, a 1MB 20ns DRAM with ECC, 134kb TAG array, and cache control logic. CPU bus data rate is 1.6GB/s. A 32-entry zero wait-state line buffer permits hit rates up to 80%.
23.3 A 7.68GIPS 3.84GB/s 1W Parallel Image-Processing RAM Integrating a 16Mb DRAM and 128 Processor Elements (2:00)
Y. Aimoto, T. Kimura, Y. Yabe, H. Heiuchi, Y. Nakazawa,
M. Motomura, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa,
H. Nobusawa, K. Koyama
NEC Corp., Sagamihara, Japan
A 2.5V image-processing RAM integrates 128 8b processing elements with 128 128kb DRAM arrays on a 314mm2 die using 0.38um CMOS. Total processor element gate count is 700k. The RAM utilizes paged-segmentation access, clocked low-voltage data-line swing, and multi-phase synchronization control.
BREAK (2:30)
23.4 A 2.5ns Clock Access 250MHz 256Mb SDRAM with Synchronous Mirror Delay (2:45)
T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, E. Kakehashi, J. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine(1), M. Igeta(1), N. Nakanishi(1), T. Itani, K. Yoshida, et al.
NEC Corp., Sagamihara, Japan
(1)NEC IC Microcomputer Systems, Ltd., Sagamihara, Japan
A 256Mb Synchronous DRAM delivers up to 1GB/s data rate and 2.5ns clock access time with a 3.3V supply. It employs a synchronous-mirror-delay circuit for internal/external clock synchronization and a prefetched pipeline with a FIFO buffer. The chip is 246mm2 and the array efficiency is 60.2%.
23.5 A 1.6GB/s 1Gb SDRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture (3:15)
Y. Nitta, N. Sakashita, K. Shimomura, F. Okuda, S. Yamakawa, A. Furukawa, K. Kise, H. Watanabe, Y. Toyoda, T. Fukada, M. Hasegawa, M. Tsukude, K. Arimoto, S. Baba, Y. Tomita, S. Komori, K. Kyuma, H. Abe
Mitsubishi Electric Corp., Itami, Japan
A 1.8V 1Gb Synchronous DRAM achieves 1.6GB/s performance at 200MHz. Implementing built-in self-test with margin-test capability, this x64 chip employs a 196 pin-ball-grid array package. A 0.29mm2 cell and 582mm2 die result from using 0.15um CMOS technology.
23.6 A 32-Bank 1Gb DRAM with 1GB/s Bandwidth (3:45)
J-H. Yoo, C-H. Kim, K-C. Lee, K-H. Kyung, S-M. Yoo, J-H. Lee, M-H. Son, J-M. Han, B-M. Kang, E. Haq, S-B. Lee, J-H. Sim, J-H. Kim, B-S. Moon, K-Y. Kim, J-G. Park, K-P. Lee, K-Y. Lee, K-N. Kim, S-I. Cho et al.
Samsung Electronics, Co., Ltd., Yongin-Gun, Korea
A 2V synchronous DRAM employs merged multibank architecture, source-synchronous I/O, and block redundancy. Capacitance of the 0.334um2 one-cylindrical-stacked cell is 25fF using a Ta2O5 dielectric. The 652mm2 non-stitched chip uses a 0.16um 4-poly, 4-metal CMOS process.
CONCLUSION (4:15)
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