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Chair: W. Bowhill, Digital Equipement Corp., Hudson MA
Associate Chair: J. Slager, Hitachi Micro Systems, Inc., San Jose, CA
22.1 A Dual Floating-Point Coprocessor with FMAC Architecture (1:00)
C. Heikes, G. Colon-Bonet
Hewlett-Packard Company, Fort Collins, CO
Circuitry in the floating-point multiply accumulate (FMAC) unit of the PA-8000 is described. This chip contains two complete FMAC units using full dual-rail domino circuitry. The shifter circuits are described as well as the at-speed serial-scan test circuitry. choices in logic and wiring layout increase noise immunity of dynamic logic.
22.2 200MHz Superscalar RISC Processor Circuit Design Issues (1:30)
N. Vasseghi
Silicon Graphics, Inc., Mountain View, CA
Selected functional blocks of a 5-way superscalar, dynamic issue, 64b RISC microprocessor include clock and power distribution for a 0.35um 6.8M-transistor, 16.6x17.9mm2, 30W chip. Solutions to latch data-feedthrough, long-wire delay, and dynamic-logic noise issues are addressed.
22.3 A Dual-Execution Pipelined Floating-Point CMOS Processor (2:00)
J. Kowaleski Jr., G. Wolrich, T. Fischer, R. Dupcak, P. Kroesen,
T. Pham, A. Olesin
Digital Equipment Corp., Hudson, MA
A floating-point processing unit for a 0.35um CMOS VLSI microprocessor has two parallel pipelines that implement both IEEE and VAX data formats, each within 4 cycles of latency. Static load circuits are combined with precharged logic for the carry-select generation. At 433MHz, it executes 866M floating point operations per second (peak).
BREAK (2:30)
22.4 A 64-Entry, 167MHz, Fully-Associative TLB for a RISC Microprocessor (2:45)
E. Anderson
Sun Microsystems, Inc., Mountain View, CA
An embedded translation look-aside buffer (TLB) has special hardware features to optimize the virtual-memory system of a 64b RISC processor. It translates a 44b virtual address to a 41b physical address every 6ns. This TLB supports variable page sizes, page and context invalidation, and memory protection via a 13b CPU context match.
22.5 A Subnanosecond 0.5um 64b Adder Design (3:15)
S. Naffziger
Hewlett Packard Company, Fort Collins, CO
A subnanosecond 64b adder implementation in 0.5mm CMOS forms the basis for a microprocessor integer and floating-point units. Integrating dual-rail dynamic logic and Ling's equations, the adder contains 7k transistors in 0.246mm2. It executes a full 64b add and latches the result in under 1ns at nominal conditions.
22.6 A 4.3ns 0.3um 54x54b Multiplier Using Precharged Pass-Transistor Logic (3:45)
M. Hanawa, K. Kaneko, T. Kawashimo, H. Maruyama(1)
Hitachi Ltd, Tokyo, Japan
(1)Hitachi ULSI Engineering, Tokyo, Japan
A multiplier has a 4.3ns latency at 2.5V and occupies 17mm2 in 0.3um CMOS process with four levels of metal. The multiplier contains a 54x54b carry-save adder tree and a 108b carry-propagate adder. It uses precharged pass-transistor circuits for the 4:2 compressor of a Booth-encoded Wallace tree.
CONCLUSION (4:15)
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