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Chair: A. Abidi, Univ of California, Los Angeles, CA
Associate Chair: B. Razavi, AT&T Bell Labs, Holmdel,NJ
19.1 A Monolithic Low-Power 16b 1MSample/s Self-Calibrating Pipeline ADC (8:30)
M. Mayes, S. Chin
National Semiconductor, Santa Clara, CA
A 20-stage pipeline architecture employs an on-chip 32b microcontroller to correct nonlinearities. Noise from digital crosstalk is reduced through timing. Fabricated in 1mm BiCMOS, the prototype dissipates 200mW from 5V and occupies 5.7x6.1mm2.
19.2 A 2.5V 12b 5MSample/s Pipelined CMOS ADC (9:00)
P. Yu, H-S. Lee
MIT, Cambridge, MA
A 12-stage pipeline architecture incorporates commutative feedback-capacitor switching and op-amp sharing to achieve 12b resolution at 5MSample/s with 33mW dissipation. Fabricated in 1.2um CMOS, the circuit occupies 4.1x4.2mm2.
19.3 A 12b 10MHz 250mW CMOS ADC (9:30)
S-I. Lim, S-H. Lee(1), S-Y. Hwang(1), C-D. Lee(2)
Seokyeong Univ., Seoul, Korea
(1)Sogang Univ., Seoul, Korea
(2)Korea Electronics Technology Inst., Kyonggi, Korea
A 4-stage pipeline architecture digitally calibrates the 4b binary capacitor DAC in the first stage to achieve 12b linearity and 10MHz sampling rate. Fabricated in 0.8um CMOS, the ADC occupies 4.2x3.6mm2 and dissipates 250mW at 10MHz with a 5V supply.
BREAK (10:00)
19.4 An 80MHz 80mW 8b CMOS Folding A/D Converter with Distributed T/H Preprocessing (10:15)
A. Venes, R. van de Plassche
Philips Research Labs, Eindhoven, The Netherlands
A folding-and-interpolation A/D converter attains 47.5 dB SINAD while dissipating 80mW from 3.3V. The chip occupies 0.3mm2 in 0.5um CMOS.
19.5 A 200MSample/s 6b Flash ADC in 0.6um CMOS (10:45)
J. Spalding, D. Dalton
Analog Devices, Limerick, Ireland
A 2.7mm2 A/D converter implemented in 0.6µm CMOS attains a linearity of 5 effective bits at the Nyquist frequency, and dissipates 377mW from 5V. The circuit features a controllable asymmetric characteristic, offset-adjust DAC, and sparkle suppression.
19.6 A 1.5V 8b 8mW BiCMOS Video A/D Converter (11:15)
H. Hasegawa, M. Yotsuyanagi, M. Satoh, S. Kishi, M. Ishida, M. Yamaguchi
NEC Corporation, Kanagawa, Japan
A 4-stage pipelined A/D converter attains 8b linearity at a 12MHz conversion rate. A differential voltage-pumped comparator in the quantizer and fast-settling DAC enable operation at 1.5V. The converter occupies 3.7mm2 in 0.5um BiCMOS .
CONCLUSION (11:45)
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