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DIGITAL TECHNIQUES
Chair: B. Song, University of Illinois, Urbana, IL
Associate Chair: K. Taniguchi, Osaka University, Osaka, Japan
18.1 Complementary Adiabatic and Fully-Adiabatic
MOS Logic Families for Gigascale Integration (8:30)
V. De, J. Meindl
Georgia Institute of Technology, Atlanta, GA
These logic families provide practical circuit implementations of quasi-adiabatic and quasi-adiabatic-reversible computing and promising alternatives to CMOS logic for low-power gigascale integration systems. The adiabatic logic families offer 1.6x to 10x more energy-efficient computation than CMOS over five generations of technology.
18.2 Elastic-Vt CMOS Circuits for Multiple On-Chip Power Control (9:00)
M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, M. Yamashina
NEC Corp., Sagamihara, Japan
A circuit technique that is insensitive to device parameter changes controls power consumption of individual subblocks without requiring triple wells or multiple thresholds. Experimental results of 16b adder, 4kb SRAM, and 100MHz PLL in 0.35um CMOS demontrate both speed improvement and power reduction at 1.5V.
18.3 A Charge Recycling Differential Logic for Low-Power Applications (9:30)
B-S. Kong, J-S. Choi, S. Lee, S-J. Lee
Korea Advanced Inst. of Science and Technology, Taejeon, Korea
This precharge technique reduces power consumption in charge recycling differential logic but maintains the speed comparable to conventional dynamic logic circuits. Experimental results exhibit 20-54% improvement in power-delay product compared with differential cascode voltage-switch logic.
BREAK (10:00)
18.4 Advances in Neuron-MOS Applications (10:15)
T. Shibata, T. Nakai, N. Yu, Y. Yamashita, M. Konda, T. Ohmi
Tohoku University, Sendai, Japan
Neuron-MOS circuits with multiple inputs facilitate real-time signal processing and analog computation. System capabilities are demostrated in three examples: offset-canceled op amp, two-dimentional motion detector that finds the movement of an image in a few 100s of ns, and analog correlator that searches a minimum-distance vector from an analog EEPROM memory.
18.5 A 16cm2 Monolithic Multiprocessor System Integrating 9 Video Signal-Processing Elements(10:45)
J. Otterstedt, K. Gaedke, K. Hermann, M. Kuboschek, H-U. Schroeder, A. Werner(1)
University of Hannover, Hannover, Germany
(1)Philips Semiconductor, Hamburg, Germany
A 16.6 cm2 IC that includes 9 programmable video signal processors uses 0.8um CMOS. Exploiting built-in self-test and redundancy concepts in the prototype, 6 processing elements per chip are functional at 66MHz, providing a peak arithmetic performance of 6GOPS per chip.
18.6 A BiCMOS Active Substrate Probe Card Technology for Digital Testing (11:15)
M. Zargari, J. Leung, S. Wong, B. Wooley
Stanford University, Stanford, CA
A card employing polyimide membrane formed on silicon substrate and implemented in 2um BiCMOS is used to probe minimum-sized CMOS inverters. A multi-channel digital tester utilizes a time digitizer with 90ps timing resolution.
CONCLUSION (11:45)
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