Go back to the ISSCC page
Chair : A. Kanuma, Toshiba Corp., Kawasaki, Japan
Associate Chair : E. Murthi, Philips Semiconductor, Sunnyvale, CA
17.1 An Offset-Free LPF for p/4-Shift QPSK Signal Generator (8:30)
H. Tanimoto, T. Itakura, T. Ueno, A. Yasuda, K. Oda
Toshiba Corp., Kawasaki, Japan
An intrinsically offset-free third-order active-RC LPF has 200kHz cut-off. A p/4- QPSK signal generator for the Japanese Personal Handy-Phone System (PHS) includes the LPFs in 0.6mm CMOS. It operates from a 2.7V power supply and dissipates 45mW. The die is 2.0x2.1mm2.
17.2 A 12mA Triple-Conversion Receiver Chipset for GPS (9:00)
F. Piazza, Q. Huang
Swiss Federal Institute of Technology, Zurich, Switzerland
A triple-conversion superheterodyne receiver for the Global Positioning System uses a 1.0um BiCMOS technology. The receiver comprises a 1.6GHz front-end, a 180MHz 1st IF, a 4.7MHz 2nd IF with on-chip RC active filter, a 1.05MHz 3rd IF and a PLL. The total current is about 12mA at 3V.
17.3 A GaAs Broadcast Satellite Tuner IC (9:30)
R. J. Bayruns, O. Lopez, S. Sweeney, K. Li, N. Ditrick
Anadigics, Inc., Warren, NJ
A broadcast satellite tuner IC with an IIP3>+10dBm and 20dB AGC range uses a bootstrapped GaAs FET. The noise figure over the full RF band of 950MHz-2150MHz is less than 7dB. The circuit contains an LNA-AGC-mixer-oscillator and draws 50mA from a +5V supply. The chip is 0.37mm2 in a low-power GaAs MESFET technology and is packaged in an SOIC-16 package.
BREAK (10:00)
17.4 A 660MB/s Interface Megacell Portable in 0.3um-0.7um CMOS ASIC (10:15)
K. Donnelly, Y-F. Chan, J. Ho, C. Tran, S. Patel, B. Lau, J. Kim, P. Chau, C. Huang, J. Wei, L. Yu, R. Tarver, M. Johnson
Rambus Inc., Mountain View, CA
A byte-wide I/O cell with 660MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear-amplifier input receiver. The CAD allows the design to be ported to CMOS processes ranging from 0.7um to 0.3um. The chip is 0.9x3.4mm2 using 0.3um rules.
17.5 A 1.4Gbps x 12-Channel Parallel Laser Diode Driver IC for Optical Interconnections (10:45)
T. Umeda, K. Yoshihara, M. Konno, K. Kaminishi, K. Hirakawa
Toshiba Corp., Kawasaki, Japan
A 12-channel parallel laser diode driver IC provides retiming of data skew among channels and temperature compensation for the laser diode output. The aggregate throughput up to 16.8Gb/s is achieved by suppressing ringing and crosstalk noise. The die is 2.5x3.5mm2 using 15GHz fT Si bipolar process. The power consumption is 4.2W at 5V.
17.6 A 10b 120MSample/s Multiple Sampling Single-Conversion CMOS A/D Converter for I/Q Demodulator (11:15)
J-E. Eklund, R. Arvidsson(1)
Linkoping University, Linköping, Sweden,
(1) Ericsson Microwave Systems AB, Molndal, Sweden
An A/D converter for IQ demodulation with analog mirror signal suppression filter in the sampling unit uses double-metal 0.8um CMOS. The circuit goes directly from a 30MHz signal to digitized I and Q values in the base band with an accuracy of 10b. The output data rate is 2MHz and the power consumption is 270mW at 5V.
CONCLUSION (11:45)
Go back to the SSCS page
If you have any comments for the ISSCC, please forward them to
Comments related to the maintenance of this web site should be sent to sscs@eecg.toronto.edu .