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MEMORY
Chair: G. Gulak, University of Toronto, Ontario, Canada
Associate Chair: K. Kimura, Hitachi Central Research Lab, Tokyo, Japan
16.1 Implementing Application-Specific Memory (1:30)
R. Foss
MOSAID Technologies Inc., Ontario, Canada
The cost-performance benefits of integrating logic and memory in a standard ASIC or memory process is reviewed. For example, in adding a DRAM macro to a 0.5um ASIC process a DRAM demanding no additional process steps achieves a 10x improvement in density over synthesized SRAM and a 5x improvement over embedded SRAM. Several other case studies are reviewed.
16.2 A 768k Embedded DRAM for a 1.244Gb/s ATM Switch in an 0.8um Logic Process (2:00)
P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow(1), K. Akeyama(2), K. Keida(2)
MOSAID Technologies Inc., Ontario, Canada
(1)Newbridge Networks Corp., Ontario, Canada
(2)Kawasaki Steel Corp., Chiba, Japan
A 256kb DRAM macrocell with 7.4x6.5um2 1-T p-channel cell in a 0.8um single- poly, double-metal logic process measures 2.4x7.8mm2. A 32b I/O port achieves 235MB/s bandwidth in page mode. Three macrocells are used as a 768kb queue memory for a 1.244Gb/s ATM switch ASIC.
16.3 One-Transistor-Cell Multiple-Valued CAM for a Collision Detection VLSI Processor (2:30)
T. Hanyu, N. Kanagawa, M. Kameyama
Tohoku University, Sendai, Japan
A content-addressable memory (CAM) based on multiple-valued logic uses a single floating-gate MOS transistor array. The 4-valued cell measures 18.48um2, occupies 14% of the area of a dynamic binary CAM, using 0.8um CMOS technology. A 356kb CAM and 7 processing elements are used in an 11.5x11.8mm2 collision detection VLSI.
BREAK (3:00)
16.4 A Single-Electron-Memory Integrated Circuit for Giga-to-Tera Bit Storage (3:15)
K. Yano, T. Ishii, T. Sano(1), T. Mine, F. Murai, K. Seki
Hitachi Central Research Lab., Tokyo, Japan
(1)Hitachi Device Engineering Corp., Tokyo, Japan
An 8x8b single-electron memory array is organized using ladder-shaped poly-silicon lines. All the cells on a word line are simultaneously erased/written/read just like flash memories. Storing fewer electrons allows for a 100x faster 10ms write/erase time and 10^6 cycle endurance.
16.5 A True Nonvolatile Analog Memory Cell Using a Coupling Charge Balancing Scheme (3:45)
K-h. Kim, K. Lee
Korean Advanced Inst. of Science and Technology, Taejeon, Korea
A nonvolatile analog memory cell uses hard-wired continuous-time feedback with a coupling charge balancing scheme. A 680um2 cell using 1.2um double-polysilicon CMOS process with 25nm tunneling gate oxide exhibits 7b resolution with 8ns programming speed.
16.6 A 2.5V 256-Level Non-Volatile Analog Storage Device Using EEPROM Technology (4:15)
H. Van Tran, T. Blyth, D. Sowards, L. Engh, B. Nataraj, T. Dunne, H. Wang, V. Sarin, T. Lam, H. Nazarian, G. Hu
Information Storage Devices, Inc., San Jose, CA
A 480k memory, storing multilevel analog voltages operates from a 2.5V to 5.5V supply. The IC stores 256-level analog voltages with ~7.5mV resolution per level, and contains a serial peripheral interface along with other circuits that allow a microphone and 8W speaker to be directly connected. The 37.4mm2 die is in 0.8um EEPROM.
CONCLUSION (4:45)
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