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Chair: M. Hatamian, Silicon Design Experts, Inc., Morganville, NJ
Associate Chair: E. Roza, Philips Research Labs, Eindhoven, The Netherlands
15.1 A Real-time Motion Estimation and Compensation LSI for MPEG2 Video Encoding (1:30)
K. Suguri, T. Minami, H. Matsuda, R. Kusaba, T. Kondo, R. Kasai, T. Watanabe, H. Satoh, N. Shibata, Y. Tashiro, T. Izuoka, H. Yamauchi, H. Kotera
NTT, Atsugi, Japan
A 3.3V 0.5um CMOS motion-estimator chip uses 3-step hierarchical telescopic-search algorithms, handling a maximum search range of 32x32 pixels for MPEG2 SP @ ML applications. It integrates 2M transistors on a 16.5x16.5mm2 die and dissipates 3.5W at 3.3V and 81MHz.
15.2 A Programmable Audio/Video Processor for H.320, H.324, and MPEG (2:00)
D. Brinthaupt, J. Knobloch, J. Othmer, B. Petryna, M. Uyttendaele
AT&T Bell Labs, Holmdel, NJ
A programmable audio/video codec chip performs all processing necessary for H.324 and H.320 video-teleconferencing, MPEG-1 video and audio decode, and MPEG-1 video encode. The 10.4x10mm2 2.27M transistor, 0.5um CMOS device achieves 16GOPS using 3W at 3.3V and 67MHz.
15.3 A 14GOPS Programmable Motion Estimator for H.26X Video Coding (2:15)
H-D. Lin, A. Anesko, B. Petryna
AT&T Bell Labs, Holmdel, NJ
A 3.3V 0.5um CMOS chip supports multiple motion-estimation algorithms, offers 14GOPS peak processing power at 66MHz and contains 162k devices in a core active area of 8.36mm². It dissipates 0.3W at 3.3V and 66MHz. It includes a dual-addressing memory and a block-rotating PE array.
15.4 A Video Signal Processor for Motion-Compensated Field- Rate Upconversion in Consumer Television (2:30)
B. De Loore, P. Lippens, P. Eeckhout, H. Huijgen, A. Löening,
M. McSweeney, M. Verstraelen, B. Pham, G. de Haan, J. Kettenis
Philips GmbH., Hamburg, Germany
Four video signal processors, integrated on a 97mm² 0.8um-CMOS chip perform motion-compensated upconversion for 100Hz TV display applications. The chip contains 980k transistors, has a processing power of 10GOPS, and 25Gb/s memory bandwidth. It dissipates 1.8W at 5V and 33MHz.
BREAK (3:00)
15.5 A 64-Point Fourier-Transform Chip for Digital Television Applications (3:15)
C. Hui, T. Ding, R Woods, J.McCanny, B. Devlin(1), A. Major(1)
Queens Univ. of Belfast, Belfast, Northern Ireland
(1)Snell and Wilcox, Petersfield, England
A 0.6um CMOS chip implements a 64\-point Fourier transform for digital TV-standards conversion. It integrates 500k transistors on a 0.8x8.0mm2 die, dissipates 0.9W at 3.3V and 27MHz, and performs the equivalent of 3.5 billion multiplications and additions per second. Two chips cascaded implement a 2D-FFT operation.
15.6 A Single-Chip Multimedia Audio System with Digital Sample-Rate Conversion and FM Sound Synthesis (3:45)
S. Bernadas, M. Alexander, J. Bian, G. Chowdhury, Q. Dong, M. Gentry, A. Goyal, M. Jaric, M. Jenkins, M. Kent, R. Malcolm, P. Matthews, K. McLaughlin, M. Munuswamy, K. Prihadi, M. Rovner, J. Scott, K. Subramoniam, W. Wagner, J. Wu
Crystal Semiconductor Corp., Austin, TX
A mixed-signal multimedia audio-system chip provides full mixing, sample-rate conversion, sound synthesis, and effects processing in the digital domain. The device in 0.6um single-poly, triple-metal CMOS measures 7x8mm2. It contains 24k analog and 816k digital transistors, requires no external glue logic, and dissipates 600mW at 5V.
15.7 5.4GOPS Linear-Array-Architecture DSP for Video Format Conversion (4:15)
M. Kurokawa, A. Hashiguchi, K. Nakamura, H. Okuda, K. Aoyama, T. Yamazaki, M. Ohki, M. Soneda, K. Seno, I. Kumata, M. Aikawa, H. Hanaki, S. Iwase
Sony Corporation Research Center, Tokyo, Japan
A 3.3V 0.4um-CMOS DSP for video- conversion of HDTV and SDTV signals contains 4,320 parallel-processing elements in a linear array. It integrates 12M transistors on a 15.12x14.95mm2 die. The peak processing power is 5.4GOPS at 50MHz. The chip dissipates 0.53W/GOPS at 3.3V.
15.8 A Complete AM/FM Stereo Receiver and Tuning System on a Single Chip (4:45)
K. Kianush
Philips Semiconductors, Eindhoven, The Netherlands
A single-chip electronically-tuned AM/FM stereo receiver uses a local-controller circuit in its tuning system. The 12.7mm² chip is implemented in 2.5um BiCMOS operates from 2.1V to 12V. The tuning circuit draws 1mA at 2.1V.
CONCLUSION (5:15)
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