Go back to the ISSCC page
MICROPROCESSORS
Chair: P. Bosshart, Texas Instruments, Dallas, TX
Associate Chair: D. Cox, IBM, Rochester, MN
13.1 A Quad-Issue Out-of-Order RISC CPU (1:30)
J. Lotz, G. Lesartre, S. Naffziger, D. Kipp
Hewlett Packard, Fort Collins, CO
A 64b 4-way superscalar PA-RISC microprocessor with full out-of-order execution produces 360SPECInt92 and 550SPECfp92. Specialized latching and clock circuits as well as extensive use of dynamic logic-enable operation up to 250MHz. 3.8M logic transistors are integrated on a 17.7x9.1mm2 die in a 3.3V 0.5um CMOS process.
13.2 A 56-Entry Instruction-Reorder Buffer (2:00)
N. Gaddis, J. Butler, A. Kumar, W. Queen
Hewlett Packard, Fort Collins, CO
Features of the 850k-transistor reorder buffer are described, including circuits for dependency tracking and launch arbitration, as well as their area/performance tradeoffs. The buffer tracks the insertion, launch and retirement of up to 4 instructions per clock cycle.
13.3 A 160MHz 32b 0.5W CMOS RISC Microprocessor (2:30)
J. Montanaro, R. Witek, K. Anne, A. Black, E. Cooper, D. Dobberpuhl, P. Donahue, J. Eno, A. Farell, G. Hoeppner, D. Kruckemyer, T. Lee(1), P. Lin, L. Madden, D. Murray, M. Pearce, S. Santhanam, K. Snyder, R. Stephany, S. Thierauf
Digital Equipment Corp. Austin, TX
(1)Stanford University, Stanford, CA
A 32b 160MHz/215MHz custom VLSI ARM microprocessor contains 2 16kB 32-way set-associative caches for instructions and data. The 2.1M-transistor chip is fabricated in a 2.0V 0.35um 3-layer-metal CMOS process. It dissipates 0.5W at 160MHz for 1.5V, and 1.1W at 215MHz for 2.0V.
BREAK (3:00)
13.4 A Multimedia 32b RISC Microprocessor with 16Mb DRAM (3:15)
T. Shimizu, J. Korematu, M. Satou, H. Kondo, S. Iwata, K. Sawai, N. Okumura, K. Ishimi, Y. Nakamoto, M. Kumanoya, K. Dosaka, A. Yamazaki, Y. Ajioka, T. Urabe, J. Hinata, K. Saitoh
Mitsubishi Electric Co., Itami, Japan
A 32b microprocessor is integrated with a 16Mb DRAM on a 19.9x7.7mm2 die. This 17M-transistor chip includes a multiplier and accumulator, 128b 66MHz internal and 16b 16.67MHz external bus. It uses a 0.45mm double-metal 3.3V CMOS technology.
13.5 A 200MHz 2.5V 4W Superscalar RISC Microprocessor (3:45)
H. Sanchez, L. Eisen(1), C. Croxton, A. Piejko, C. Nicoletta, I. Vo(1), B. Branson, W. Wang(1), Q. Nguyen(1), T. Buti(1), L. Hsu(1), M. Saccamango(1), S. Ratanaphanyara(1), R. Philip(1), J. Alvarez, S. Weitzel(1), G. Gerosa
Motorola Inc., Austin, TX
(1) IBM, Austin, TX
A 2.6M-transistor, 81mm2 die includes two 16kB 4-way set-associative caches and 5 execution units. Compared to an earlier implementation, this processor runs at 2x the frequency with only 33% higher power. The chip dissipates 40mW in sleep mode.
13.6 A Multimedia-Enhanced X86 Microprocessor (4:15)
F. Norrod, B. Briggs, R. Perego, B. Falardeau, C. Wilcox, R. Wawryznek, W. Walker, B. Arnold, C. Peterson S. Mendyke, J. Baldwin, B. Cain, E. Behnke, D. Neuchterlein, K. Fanjoy, F. Dunlap, B. Gullette, C. Schrepel, R. Mueller, R. French, A. Harris, T. Heller
Cyrix Corp., Longmont, CO
This microprocessor includes a CPU core, a DRAM controller, a graphics accelerator and a PCI interface. The 16kB unified L1 cache and the integer unit include features to accelerate graphics and multimedia applications. The 2.4M-transistor die measures 11.6x13.8mm2 and operates at 120MHz.
13.7 A 433MHz 64b Quad-Issue RISC Microprocessor (4:45)
P. Gronowski, P. Bannon, M. Bertone, R. Blake-Campos, G. Bouchard, W. Bowhill, D. Carlson, R. Castelino, D. Donchin, R. Fromm, M. Gowan, A. Jain, B. Loughlin, S. Mehta, J. Meyer, R. Mueller, A. Olesin, T. Pham, R. Preston, P. Rubinfeld
Digital Equipment Corp., Hudson, MA
A custom-VLSI microprocessor has an estimated performance greater than 500SPECint92. The 9.6M-transistor die measures 14.5x14.4mm2 and dissipates less than 25W. The chip is fabricated in a 2.0V 0.35um 4-layer-metal CMOS.
CONCLUSION (5:15)
Go back to the SSCS page
If you have any comments for the ISSCC, please forward them to
Comments related to the maintenance of this web site should be sent to sscs@eecg.toronto.edu .