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Chair: R. Walker, Hewlett-Packard Labs, Palo Alto, CA
Associate Chair: J. Ewen, IBM T.J. Watson Research Center, Yorktown Heights, NY
12.1 NRZ Timing-Recovery Technique for Band-Limited Channels (1:30)
B-S. Song, D. Soo(1)
Coordinated Science Lab. University of Illinois, Urbana, IL
(1)Chrontel Inc. San Jose, CA
A decision-feedback-equalizer-based timing-recovery technique uses a data-triggered phase detector to sustain phase locking through 500 consecutive missing transitions. 30Mb/s NRZ data transmitted over a 3MHz channel is recovered with 2NS peak-to-peak clock jitter using 2um CMOS. The 1mm2 chip dissipates 55mW from 5V.
12.2 A 143-360Mb/s, Auto-Rate Selecting, Data-Retimer Chip for Serial-Digital Video Signals (2:00)
D. Potson, A. Buchholz
Comlinear Corp., Fort Collins, CO
A PLL recovers clock from serial scrambled NRZI digital video at 143, 177, 270 and 360Mb/s, depending on the video . The appropriate frequency band is automatically selected while avoiding harmonic lock. Center-frequency process variation is removed at wafer probe. The 4mm2 chip core in 0.8um 14GHz BiCMOS dissipates 500mW from 5V.
12.3 A 622Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array (2:30)
I. Lee, C. Yoo, S. Chai(1), W. Song, W. Kim
Seoul National University, Seoul, Korea
(1)Electronics and Telecommunications Research Instit., Daejeon, Korea
A 622 Mb/s clock-recovery PLL for SDH/SONET uses a 0.8um CMOS technology. A time-interleaved phase detection scheme is used, and all PLL blocks operate at 78MHz. The chip core is 800x900um2 and dissipates 200mW with 5V supply. RMS jitter of the recovered 78MHz clock is 46ps (0.36%).
BREAK (3:00)
12.4 A 0.8um CMOS 2.5Gb/s Oversampling Receiver for Serial Links (3:15)
C-K. Yang, M. Horowitz
Stanford University, Stanford, CA
A receiver for OC-48 (2.488Gb/s) serial data uses 0.8um CMOS. Gate speed limitations are overcome using 1:8 demultiplexing at the receiver. To perform clock recovery, data is 3x oversampled. The oversampled outputs are processed to reconstruct the data bits. The 3x3mm2 test chip dissipates 2.25W at 5V.
12.5 A 10Gb/s BiCMOS Clock and Data-Recovering 1:4 Demultiplexer in a Standard Plastic Package with External VCO (3:45)
J. Hauenschild(1), C. Dorschky, T. von Mohrenfels, R. Seitz
Philips Kommunikations Industrie, Nürnberg, Germany
(1)Now at National Semiconductor GmbH, Fürstenfeldbruck, Germany
A 10Gb/s clock and data recovery circuit with 1:4 demultiplexer is fabricated in a 0.7mm single-poly 16GHz BiCMOS process. The associated 1:2 DMUX and parallel early-late phase detector are supplied with 5GHz clocks from an external VCO. The plastic package does not measurably degrade the differential input data reflection. The 2.3x2.3mm2 chip dissipates 450mW from -3.6V.
12.6 Circuit Techniques for 10 and 20Gb/s Clock Recovery Using a Fully-Balanced Narrowband Regenerative Frequency Divider with 0.3um HEMTs (4:15)
Z.-G. Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hülsmann, K. Köhler, B. Raynor, J. Schneider, D. Briggmann(1)
Fraunhofer-Institute for Applied Solid-State Physics, Freiburg, Germany
(1)FTZ, German Telecom AG, Darmstadt, Germany
A dual-mode clock-recovery IC uses a current-mode XOR to drive a tank circuit tuned to the bit rate, or twice the bit rate, along with a fully-balanced narrowband regenerative frequency divider. The 2x2mm2 chip operates at 10 and 20Gb/s, dissipating 200mW at -3V.
12.7 A 10Gb/s Silicon Bipolar IC for PRBS Testing (4:45)
O. Kromat, U. Langmann, G. Hanke(1), W. Hillery(2)
Ruhr-Universität Bochum, Bochum, Germany
(1)Deutsche Telekom AG, Darmstadt, Germany
(2)Hewlett-Packard Company, Palo Alto, CA
Dual-output maximal-length PRBS sequences of 215-1 and 223-1 bits are generated up to 10Gb/s, following the CCITT standard. Errors in incoming sequences are detected and counted. Word-synchronization is performed between two chips, allowing for external 4:1 multiplexing up to 40Gb/s. The 4x8mm2 chip dissipates 6.2W from 5V.
CONCLUSION (5:15)
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