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FE7 The Interconnect Nightmare
Don Draper, NexGen, San Jose, CA.
Organizer: Jeff Yetter, Hewlett-Packard Co, Fort Collins, CO
Advances in device size and characteristics have not been matched by advances in interconnect performance and density. Consequently, gate delays have diminished relative to wiring delays to the point that gate delays are often negligible. In addition, noise from coupling and supply loops presents increasingly difficult design challenges. More layers of interconnect, thicker interconnect, and thicker dielectrics offer temporary remedies, but no long-term solution.
Panel: Donald A. Priore, Digital Equipment Corp., Hudson, MA
Charlie X. Huang, EPIC Design Technology Inc., Santa Clara, CA
Michael A. Buckley, Hewlett-Packard Co., Fort Collins, CO
Yusuke Ohtomo, NTT LSI Labs, Kanagawa, Japan
Jurij Paraszczak, IBM T.J. Watson Research Center Yorktown Heights NY
Ahsan Bootehsaz , Synopsys, Inc., Mountain View, CA
Eric P. Finchem, TriQuint Semiconductor, Inc., Beaverton, OR
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