Go back to the ISSCC page
FE5 What is the best signalling technology for memory to logic chip communications?
Moderator/Organizer: Richard Crisp, Rambus, Mountain View, CA
Computer system performance and memory component density continue to scale. Advances in integration reduce system component count. I/O toggle rates must increase to manage the pin count explosion. Long-used signalling technologies appear incapable of operating above 100MHz. Signalling technologies proposed to carry the industry into the next century include HSTL, SSTL, CTT, GTL, RSL and improved LVTTL. The problem is delivering at the lowest cost, high toggle rates, signal integrity and low power while not precluding expandability.
Panel: David Chapman, Motorola Semiconductor, Austin, TX
Richard C. Foss, Mosaid Technologies, Kanata, Canada
Terry Lee, Micron Technology, Boise, ID
Tom Lee, Stanford University, Stanford, CA
Rick Luebs, Hewlett-Packard, Ft. Collins, CO
Masao Taguchi, Fujitsu Ltd., Kawasaki, Japan
Go back to the SSCS page
If you have any comments for the ISSCC, please forward them to
Comments related to the maintenance of this web site should be sent to sscs@eecg.toronto.edu .