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Chair: A. Lancaster, Motorola, Austin, TX
Associate Chair: K. Sasaki, Hitachi America, Ltd., San Jose, CA
9.1 A 6ns 1.5V 4Mb BiCMOS SRAM (8:30)
S. Kuhara, H. Toyoshima, K. Takeda, K. Nakamura, H. Okamura, M. Takada, H. Suzuki, H. Yoshida, T. Yamazaki
NEC Corp., Sagamihara, Japan
6ns access time at 180mW and 1.5V supply is achieved using boost-BinMOS gates for address decoding, optimized word-line boost; a stepped-down CML cascoded bipolar sense amplifier; and optimum-boost voltage-detection. A 2.0x4.26mm2 highly-resistive-load memory cell produces 11.3x7.1mm2.
9.2 A 400MHz 4.5Mb Synchronous BiCMOS SRAM with Alternating Bit-line Loads (9:00)
A. Suzuki, T. Kobayashi, T. Hamano(1), H. Hatada, A. Kawasumi, F. Matsuoka, K. Ishimaru, M. Takahasi, M. Nishigohri, Y. Okayama, Y. Unno(1), M. Kakumu, J. Tsujimoto
Toshiba Corp., Kawasaki, Japan
(1)Toshiba Microelectronics Corp., Kawasaki, Japan
A 4.5Mb (x36/x18) SRAM with a two-stage pipeline structure uses a 0.3um triple-metal BiCMOS process with shallow-trench isolation. Alternating bit-line-loads reduce bit-line delay by 0.2ns (30%). The memory uses skew-compensated write circuitry and a switched delay decoder.
9.3 A 300MHz, 3.3V 1Mb SRAM in 0.5um CMOS (9:30)
H. Pilo, S. Lamphier, F. Towler, R. Hee
IBM Microelectronics Division, Essex Junction, VT
Typical access time is 5.4ns using a 3.3V 0.5um process. A dual-clock flow-through read protocol achieves a 750ps setup and hold window for all input signals. The SRAM interfaces to either HSTL or LVTTL levels. Programmable impedance HSTL output drivers match transmission line impedance within 10% over process, voltage, and temperature variations.
BREAK (10:00)
9.4 350MHz Time-Multiplexed 8-port SRAM and Word-Size- Variable Multiplier for Multimedia DSP (10:15)
T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, M. Yoshitomi, S. Kitabayashi(1), T. Higashi(1), M. Klein(2), J. Thomson(2), R. Carpenter(2), R. Donthi(2), D. Renfrow(2), L. Tinkey(2), B. Maness(2), J. Battle(2), S. Purcell(2), M. Farmwald(2), D. Burns(2), T. Sakurai
Toshiba Corp., Kawasaki, Japan
(1)Toshiba Microelectronics Corp., Kawaski, Japan
(2)Chromatic Research, Mountain View, CA
A time-multiplexed 8-port 512x72 SRAM macro with word-size-variable 18x18 multipliers in a multimedia DSP LSI operates at 87.7MHz at 3V power supply for equivalent 350MHz operation. Using 0.5mm triple-metal CMOS the memory cell is 25.8x9.2um2.
9.5 A 1V 100MHz 10mW Cache Using a Separated Bit-line Memory Hierarchy and Domino Tag Comparators (10:45)
H. Mizuno, N. Matsuzaki, K. Osada, T. Shinbo(1), N. Ooki(1), H. Ishida(1),
K. Ishibashi, T. Kure
Hitachi, Ltd., Central Research Laboratory, Tokyo, Japan
(1)Hitachi ULSI Engineering Corp., Tokyo, Japan
A 1V 2kB Level 1 / 16kB Level 2 4-way set-associative cache uses 0.25um CMOS technology with a 3.6x2.1mm2 die. 6.9ns effective latency and 10mW power consumption is obtained at 100MHz and 1V supply. Separated bit-line memory and a domino tag comparator are included.
9.6 A 2ns Zero-Wait-State 32kB Semi-Associative L1 Cache (11:15)
J. Covino, J. Connor, D. Evans, A. Roberts, M. Robillard, J. Sousa, L. Ternullo Jr.
IBM Microelectronics Division, Essex Junction, VT
A 32kB semi-associative level-1 cache in a 0.5um, 2.5V CMOS technology uses self-resetting circuits for 2ns access time. The cache consists of a data-storage-array macro, a content-addressable-memory macro, and memory built-in self-test. Access cycles include late-select generation and data formatting.
9.7 A 500MHz 288kb CMOS SRAM Macro for On-Chip Cache (11:45)
K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube,
K. Aoyama, S. Kawamura
Fujitsu Ltd., Kawasaki, Japan
A 4kx72b, 2.5V synchronous SRAM macro uses 0.25um CMOS technology for a 2ns clock access time. A two-stage clock generator provides word-size flexibility for embedded applications. The layout permits two signal layers to run over the memory array with shielding provided by interleaving with two power-supply layers.
9.8 A 256kB Second-Level Cache with 1.6GB/s Data Bandwidth (12:00)
M. Balmer, D. DiMarco, C. Freeman, K. Hose, J. Miller, E. Riggs
Intel Corp., Hillsboro, OR
A 256kB CMOS 4-way set-associative cache contains both tag and data arrays, and includes built-in self test. The memory is a companion device, with a tightly-coupled 64b data bus packaged together with the P6 processor. The SRAM uses a 0.4um Leff BiCMOS process with 4-level metal. Maximum power dissipation is 3.8W at 3.3V and 150MHz assuming back-to-back reads.
CONCLUSION (12:15)
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