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Chair: I. Young, Intel Corp., Hillsboro, OR
Associate Chair: D. Wingard, MicroUnity Systems Engineering, Sunnyvale, CA
8.1 Low-Jitter Process-Independent DLL and PLL based on Self-Biased Techniques (8:30)
J. Maneatis
Silicon Graphics, Inc., Mountain View, CA
A self-biased DLL and a PLL achieve process independence, fixed damping factor, fixed bandwidth-to-operating-frequency ratio, and input-phase offset cancellation. In a 0.5um n-well CMOS technology, the PLL operates from 0.01MHz to 275MHz and has less than 180ps/V tracking jitter sensitivity to supply noise at 133MHz.
8.2 A 320MHz, 1.5mW at 1.35V CMOS PLL for Microprocessor Clock Generation (9:00)
V. von Kaenel, D. Aebischer, C. Piguet, E. Dijkstra
CSEM SA, Neuchâtel, Switzerland
A fully-integrated 320MHz PLL generates an on-chip microprocessor clock using a VCO constructed from an active-cascode current-controlled ring oscillator together with an asynchronous variable divider chain. Implemented in a 0.35mm triple-metal CMOS process, the PLL dissipates 1.5mW from a 1.35V supply.
8.3 A 360MHz 3V CMOS PLL with 1V Peak-to-Peak Power-Supply-Noise Tolerance (9:30)
Z-X. Zhang, H. Du, M. Lee
Cirrus Logic, Inc., Fremont, CA
A PLL integrated in a 0.5mm 3.3V triple-metal CMOS process operates from 28 to 360MHz. With quiet supplies, the PLL draws 3mA at 250MHz with cycle-to-cycle jitter of less than 12ps rms and 80ps peak-to-peak. With 1V peak-to-peak sine-wave supply noise, the cycle-to-cycle jitter is less than 112ps rms and 380ps peak-to-peak.
BREAK (10:00)
8.4 A Digital Phase Aligner Macro for Clock Tree Compensation with 70ps Jitter (10:15)
M. Dina, T. Nguyen, J. Strom, D. Woeste
IBM, Rochester, MN
A 3.3V digital phase-aligner macro in 0.5um CMOS technology supports clock cycle times from 8 to 25ns. The aligner deskews clock-tree latency with up to 5 cycles of clock-tree delay. This ASIC-compatible design occupies 1.2mm2, dissipates 100mW, and achieves less than 70ps peak-to-peak phase error.
8.5 Modelling and Characterization of High-Speed Signal Propagation and Crosstalk on Long On-Chip Interconnections (10:45)
A. Deutsch, L. Terman, G. Kopcsay, C. Surovic, B. Rubin, R. Dunne, T. Gallo, R. Dennard
IBM, Yorktown Heights, NY
Analysis and experimental measurement of long on-chip interconnections demonstrate the need for distributed RLCG-parameter transmission line modelling. The fabricated test vehicles contain lines as long as 1.6cm at 0.9-4.8um line widths in a 5-metal-layer 0.5um CMOS technology.
8.6 Flow Latch and Edge-Triggered Flip-Flop Hybrid Elements (11:15)
H. Partovi, R. Burd, U. Salim, F. Weber, L. Digregorio, D. Draper
NexGen Inc., Milpitas, CA
A lower latency flip-flop increases operating frequency by 10% while reducing overall clock loading by 30%. The hybrid elements offer cycle-time-borrowing benefits of latches with edge-triggered clocking for both static and dynamic applications.
8.7 A 100MHz 0.4W RISC Processor with a 200MHz Multiply-Adder using Pulse-Register Techniques (11:45)
S. Kozu, M. Daito, Y. Sugiyama, H. Suzuki, H. Morita, M. Nomura, K. Nadehara, S. Ishibuchi, M. Tokuda, Y. Inoue, T. Nakayama,
H. Harigai, Y. Yano
NEC Ltd., Kumamoto, Japan
A 1M-transistor 118MIPS 32b RISC processor with a multiply-add unit for multimedia applications is implemented in a 0.5um 2-layer-metal CMOS technology on a 9.12x8.32mm2 die. A pulse-register with on-demand clocking achieves 200MHz 32bx32b multiply-add dissipating 4.28mW/MHz at 2.65V.
CONCLUSION (12:15)
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