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Chair: S. Roy, TranSwitch, Shelton, CT
Associate Chair: E. Rathke, GTE Labs, Waltham, MA
7.1 A Custom ASIC VLSI Device for Asynchronous Transfer Mode (ATM) (8:30)
M. Thomann
Micron Technology, Inc., Boise, ID
A single-chip solution achieves 1.391Gb/s throughput and over 100 possible port configurations for ATM multiplexing and switching systems. For switching speed and system flexibility at low cost, the chip uses expandable memories and edit buffers.
7.2 A Chip-Set Enabling B-ISDN ATM UNI Transmission Convergence (TC), AAL 3/4 Layers, and ATM Layer Functions (9:00)
J. Calderón, J. Tapia, E. Corominas1, and L. París(1)
Centre Nacional de Microelectrónica, CNM-CSIC, Barcelona, Spain
(1)Universitat Autónoma de Barcelona, Barcelona, Spain
An ATM chipset enables 155Mb/s B-ISDN. The SDH-based TC device performs framing, pointer processing, and cell delineation, consuming 2.2W at 155MHz. The segmentation and reassembly chip (SAR) supporting 155Mb/s traffic includes on-chip CAM for connection identification, consuming 3.2W at 19.44MHz in 0.8um CMOS.
7.3 A 5Gb/s 8x8 ATM Switch Element CMOS LSI Supporting 5 Quality-of-Service Classes with 200MHz LVDS Interface (9:30)
Y. Unekawa, K. Seki(1), K. Sakaue(1), A. Nakao, S. Yoshioka, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, Y. Miyazawa, T. Kuroda, Y. Kamatani, T. Sakurai, A. Kanuma, K. Fujiwara, K. Shimoda
Toshiba Corp., Kawasaki, Japan
(1)Toshiba Microelectronics Corp., Kanagawa, Japan
A 5Gb/s, 8x8 ATM switch element supports 5 quality-of-service classes including available bit rate. Link-by-link multicast is supported. The switch element uses a 200MHz CMOS low-voltage differential signal interface. The 17.5x17.5mm2 chip in 0.35um CMOS is packaged in a 447-pin CPGA.
BREAK (10:00)
7.4 A 2.5Gb/s 32:1/1:32 Multiplexer/Demultiplexer Chipset for SONET Communications (10:15)
P. McDevitt, J. McDonald, P. Pham,
Motorola Inc., Chandler, AZ
A 32:1/1:32 Mux/Demux chipset is intended for SONET OC-48 communication systems. A 2.5GHz output clock lies within 50ps of the data bit center. The bipolar chipset shows <10ps jitter on transmitted stream. The multiplexer and demultiplexer use 0.9W and 1.7W, respectively.
7.5 2.8Gb/s 176mW Byte-Interleaved and 3.0Gb/s 118mW Bit-Interleaved 8:1 Multiplexers in 0.15um CMOS
M. Kurisu, M. Kaneko, T. Suzaki, A. Tanabe, M. Togo, A. Furukawa, T. Tamura, K. Nakajima, and K. Yoshida (10:45)
NEC Corp., Kawasaki, Japan
A 2.8Gb/s byte-interleaved multiplexer and a 3.0Gb/s bit-interleaved 8:1 is intended for SONET communication systems. Interleaving, dual-output D-FFs, and clock distribution enable multi-gigahertz operation in CMOS. The chipset consumes 43mW/GHz and 20mW/GHz for byte-interleaved and bit-interleaved operation, respectively.
7.6 Gigabit Complementary HFET Communication Circuits: 16:1 Multiplexer, 1:16 Demultiplexer and 16x16 Crosspoint Switch (11:15)
G. La Rue and T. Dao
Boeing Defense and Space Group, Seattle, WA
Three integrated circuits are intended for data-communication applications in space. The mux and demux dissipate 53mW and 91mW, respectively. The crosspoint switch consumes 510mW/Gbs. The circuits use a 0.7um complementary heterojunction FET process with a 30GHz and 6GHz fT for n- and p-channel FETs, respectively.
7.7 Single-Chip 4x500Mbaud CMOS Transceiver (11:45)
A. Widmer, K. Wrenner, H. Ainspan, B. Parker, P. Austruy(1), A. Haen(1), B. Brezzo, J. Ewen, M. Soyuer, A. Blanc(1), J. C. Abbiate(1), A. Deutsch, H. Shin
IBM T. J. Watson Research Center, Yorktown Heights, NY
(1)IBM Centre d'Etudes et Recherches, La Gaude, France
Four 500Mbaud serializer/deserializer pairs on a CMOS chip packaged on a ceramic BGA reduce connector and wire congestion on a 72-wire interface by a factor of 9. Byte-level phase alignment can be programmed with 0.10-clock-cycle resolution. The 9.7x9.2mm2 die in 0.5um CMOS dissipates 3.1W at aggregate 2.0Gbaud.
CONCLUSION (12:15)
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