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Chair: K. Bindloss, Rockwell, Newport Beach, CA
Associate Chair: I. Kuroda, NEC, Kawasaki, Japan
10.1 A Low-Power Video-Rate Pyramid VQ Decoder (8:30)
E.. Tsern, T. Meng
Stanford University, Stanford, CA
A pyramid vector-quantization decoder chip delivers error-resilient video decompression at 6.7mW power level for portable, wireless applications. It operates at a 1.35 V supply to decode 1.27 Mpixels/s at 30 frames/s, and requires no external hardware support or memory.
10.2 Video Encoder/Decoder Chip Set for Digital VCRs (9:00)
K. Hasegawa, K. Ohara, A. Oka, T. Kamada, Y. Nagaoka, K. Yano, E. Yamauchi, T. Kashiro, T. Nakagawa
Matsushita Electric Co., Osaka, Japan
A video encoder/decoder 2-chip set for digital VCRs compresses a digital component video signal by a factor of approximately 6 in real time. Each chip contains 500k transistors, in 71mm2 and 79mm2, respectively in 0.5um 2-layer metal CMOS, and dissipates a total of 142mW using a 2V supply.
10.3 A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme (9:30)
T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakurai
Toshiba Corp., Kawasaki, Japan
A 2-D DCT core processor performs HDTV-resolution video compression / decompression. Threshold voltage is varied dynamically to reduce power dissipation, while maintaining 150MHz operation. It is fabricated in 0.3um triple-well double-metal technology and consumes 10mW from a 0.9V supply.
BREAK (10:00)
10.4 A 1V Multi-Threshold-Voltage CMOS DSP with Efficient Power-Management for Mobile Phone (10:15)
S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. Yamada
NTT LSI Labs., Atsugi, Japan
A digital signal processor provides 26MOPS (13MHz) at 1.1mW/MOPS using multi-threshold-voltage 0.5um CMOS (MTCMOS). It minimizes energy-delay product at 1.0V using both high- and low-threshold voltage transistors. An additional processor reduces power consumption by a factor of 10 during the waiting period.
10.5 A Programmable CODEC Signal Processor (10:45)
S. Norsworthy, L. Bays, J. Fisher
AT&T Bell Labs, Allentown, PA
A codec integrated with a 100-MIPS 16b programmable DSP provides 90dB linearity with programmable sampling rates and filter characteristics. The device is fabricated in 0.5um triple-metal double-poly CMOS and consumes 0.5mA per MIPS at 3V.
10.6 Baseband Filters for IS95 CDMA Receiver Applications Featuring Digital Automatic Frequency Tuning (11:15)
H. Khorramabadi, M. Tarsia, N. Woo
AT&T Bell Labs, Murray Hill, NJ
A 3V 0.6um CMOS chip integrates dual low-pass 7th-order continuous-time Chebychev filters for IS95 CDMA. It exhibits out-of-band IIP3 of 34dBm, output 1dB compression of 18.4dBm, input-referred noise of 35uVrms, and gain of 18dB. It achieves off-line automatic frequency tuning with no additional hardware.
10.7 An Adaptive Cable Equalizer for Serial Digital Video Rates to 400Mb/s (11:45)
A. Baker
Comlinear Corp., Fort Collins, CO
A 0.8um 14GHz BiCMOS monolithic adaptive cable equalizer synthesizes the inverse of the dispersive-loss characteristic of cables and compensates temperature and process variations. Peak-to-peak jitter at the component video rate of 270Mb/s is less than 200ps for a 200m length of Belden 8281 cable.
CONCLUSION (12:15)
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