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Objective: This course on digital television with emphasis on digital cable television systems, hardware, and signal processing functions requires no prior knowledge of the subject. Course completion provides a perspective on the importance of digital television in cable, satellite, and terrestrial digital TV systems and will understand the issues underlying the architectures, algorithms, standards, and IC designs.
Registration: (at San Francisco Marriott Hotel) (7:00 - 8:00)
The Short Course is scheduled from 8:00 to 4:30. If there is sufficient demand, a second section wisll be run from 10:00 to 6:30.
System Overview (Heegard) (8:00 - 9:30)
Compression algorithms and standards: Framing and block structures; predictive/interpolative coding; motion compensation; DCT; quantization; entropy and run-length coding; video conferencing standards; JPEG; MPEG. Video networking: Access control; multiplexing; cryptography. Transmission: Modulation basics; QAM and VSB; Receiver basics; adaptive signal processing; error control; coding; HDTV/SDTV standards.
Digital TV Receiver Systems (Hooijmans) (10:00 - 11:30)
Channel Decoding ICÕs and systems: Channel selection; down-conversion; introduction to demodulation, demodulation control, error correction, and systems loops with MPEG2 output signal. QPSK satellite receiver systems: variable vs fixed bitrate demodulation; phase noise and tilt requirements; Nyquist filtering at baseband vs IF; Low-noise block converters for down-conversion. Cable TV receivers: single vs dual conversion implementations.
Digital Demodulation, Equalization and
Error Correction (King) (13:00 - 2:00)
Signal processing functions at the physical layer of digital TV transmission from the tuner IF output to the digital transport interface. Receiver functions: Carrier recovery methods; adaptive equalization; baud timing recovery; AGC. Forward error correction: Scrambling; synchronization; trellis coding; Reed-Solomon coding; interleaving. ITU standards: DV8 (Digital Video Broadcasting, Europe) and DigiCable (US).
Architectures and Standards for Video Compression (Chan) (2:30 - 4:00)
JPEG, H.261, MPEG1, and MPEG2 video compression standards. Overview of functionalities and hardware for MPEG2 decoder modules: Video coder; system parser; video parser; inverse quantization; inverse DCT; motion compensation unit; audio compression. Other system issues: bandwidth and memory requirements; system design issues and tradeoffs; RISC/DSP vs hardwired approaches.
T. Chan is director of engineering at Cirrus Logic developing PC multi-media devices. His interests include MPEG, 3D Graphics, and PC audio. He holds a PhD from the Univ. of Arizona. He has worked with S3, Chips and Technologies, Inc., LSI Logic, Intel, and AT&T Bell Labs. He holds a patent and has several pending. He is a co-author of "VLSI Handbook".
Chris Heegard is Prof. of EE at Cornell University. He holds BS and MS from U. Massachusetts and PhD from Stanford. He teaches digital communications, error codes, information theory, detection/estimation theory, and digital systems. His research includes: coding and communication theory, algorithms for digital communications, audio/video compression, and coding for recording. He is a consultant with patents in digital HDTV and cable TV transmission. He is an IEEE Fellow.
Pieter W. Hooijmans is Head of Development at Philips Tuners in Krefeld, Germany. He holds a PhD from Delft University of Technology, The Netherlands. He spent 8 years at the Philips Research Labs, Eindhoven, working on high-bitrate coherent optical communication systems and in 1993 joined Philips Tuners Group (TV and satellite tuners, LNBs, digital, wireless, and cordless modules). He is author of a book, and over 30 publications and 9 patents.
Andrew J. King is Design Group Leader of the Integrated Systems Center of General Instrument. In the semiconductor industry for 14 years, he has developed digital transmission ICs for cable systems for four years. He has designed QAM transmission system ICs including forward error correction chip for digital set-top converters. He has lectured in UCLA short courses on VLSI design of digital transmission systems.
Registration: use ISSCC96 Registration Form on the Advance Program Centerfold.
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