Disk and Arithmetic Signal Processors

Chair: P. Ruetz, Silicon Architects, Sunnyvale, CA
Associate Chair: W. Gass, Texas Instruments, Dallas, TX

5.1 A 16MB/s PRML Read/Write Data Channel (1:30)

R. Richetta, C. Goetschel, R. Greene, R. Kertis, R. Philpott,
T. Schmerbeck, D. Schulte, D. Swart
IBM Corp., Rochester, MN

A 3.3V, 0.5mm BiCMOS mixed-signal 16MB/s 144MSample/s PRML read/write data channel provides both PRML and EPRML signal encoding. Signal equalization is provided using a programmable continuous-time low-pass filter and a 10-tap finite-impulse-response (FIR) digital filter. The 5.1mm2 chip contains 50k equivalent CMOS logic gates and analog circuits.


5.2 A 270MHz 10-Tap Digital FIR Filter for PRML Disk-Drive Read Channels (2:00)

D. Pearson, S. Reynolds, A. Megdanis, S. Gowda, K. Wrenner,
R. Galbraith*, H. Shin
T. J. Watson Research Center, IBM Corp., Yorktown Heights, NY
*Storage Systems Division, IBM Corp., Rochester, MN

A 10-tap digital FIR filter performs PR-IV PRML channel equalization at a data rate up to 270MSample/s. It uses 0.5mm BiCMOS and a distributed arithmetic filter architecture. The 4mm2 block dissipates 600mW at 200MSample/s at 3.3V.


5.3 A 240MHz 8-Tap Programmable FIR Filter for Disk-Drive Read Channels (2:30)

L. Thon, P. Sutardja, F-s. Lai, G. Coleman
IBM Almaden Research Center, San Jose, CA

A 8-tap digital FIR filter performs channel equalization at 240MSample/s data rate. The filter uses 0.8mm CMOS and a Direct Form II (transposed) architecture. The 2.9mm2 block dissipates 426mW at 240MSample/s with a 3.7V supply.


Break (3:00)


5.4 A 0.9V, 100MHz, 4mW, 2mm2, 16b DSP Core (3:15)

M. Izumikawa, H. Igura, M. Yamashina, H. Ito*, S. Wakabayashi,
K.Furuta, K. Nakajima*, T. Mogami, T Horiuchi*
Microelectronics Research Lab/*ULSI Device Development Lab,
NEC Corp., Sagamihara, Japan

A 0.25mm CMOS DSP core is composed of a 16b multiplier, a 32b adder, an 8kb SRAM and a PLL. PLL pull-in time is 0.7ms at 0.9V. Sense amplifiers are employed on internal data busses.


5.5 114 MFLOPS Logarithmic-Number-System Arithmetic Unit for DSP Applications (3:45)

D. Lewis
University of Toronto, Toronto, Canada

A DSP arithmetic core based on a logarithmic number system uses two multiplier/dividers and one adder/subtractor. IEEE-754 precision is obtained with 69k transistors in a 16mm2 1.2mm CMOS core. Three operations are performed in each 38MHz cycle.


5.6 A 210Mb/s Radix-4 Bit-Level Pipelined Viterbi Decoder (4:15)

A. Yeung, J. Rabaey
University of California, Berkeley, CA

A 16-state 210Mb/s Viterbi decoder implements a parallel radix-4 add-compare-select (ACS) architecture using bit-level pipelining. The 75k-transistor 30mm2 die dissipates 2.5W at 5V using 1.2mm CMOS technology.


5.7 An IC for "Turbo-Codes" Encoding and Decoding (4:30)

C. Berrou, P. Combelles, P. Pénard, B. Talibart
C.C.E.T.T., Cesson-Sevigne, France

This 80mm2 codec for future digital TV broadcast systems in 0.8mm 2-metal CMOS contains 600k transistors, and operates at clock rates up to 40MHz.


Conclusion (4:45)


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