Technology Directions: Displays Photonics and Ferroelectric Memories

Chair: J. Cressler, Auburn University, AL
Associate Chair: W. Yang, Harvard University, Cambridge, MA


4.1 Technology Advances in Liquid-Crystal Displays (1:30)

Y. Ishii, K. Awane
Sharp Corp., Tenri, Japan

Amorphous-silicon thin-film-transistor (TFT) technology is used to realize 21inch VGA active-matrix liquid-crystal displays (LCD) with a 40-50° viewing angle. TFT-LCD technology is expected to have 262,144 colors, with 80-120° viewing angle, and 30-inch HDTV capability by the end of the decade.


4.2 Silicon-Based Photonic Devices (2:00)

R. Soref
US Air Force Rome Laboratory, Hanscom AFB, MA

Emerging silicon optoelectronic ICs (OEICs) combine low-cost, reliable silicon-based photonics and electronics to allow monolithic integration of new silicon-germanium (SiGe) optical devices with SiGe/Si HBTs, FETs, and Si BiCMOS. Current research using bandgap engineering is expected to yield useful monolithic Si-based light sources.


4.3 Single-Transistor Ferroelectric Memory Cell (2:30)

T. Nakamura, Y. Nakao, A. Kamisawa, H. Takasu
Rohm Corp., Kyoto, Japan

A single-transistor ferroelectric memory cell is composed of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FET with a floating gate between the ferroelectric thin film and the gate oxide. The PZT thin-film ferroelectric element uses Ir/IrO2 electrodes to improve programming lifetime to 1012 cycles.


Break (3:00)


4.4 A 0.9V/100ns Embedded Ferroelectric Memory for Microcontrollers (3:15)

T. Sumi, M. Azuma, T. Otsuki, J. Gregory *, C.A. Paz De Araujo **
Matsushita Electronics Corp., Osaka, Japan/* Symetrix Corp./
** University of Colorado, Colorado Springs, CO

A methodology for embedding ferroelectric memories in microcontrollers optimizes memory-cell design for operation down to 0.9V at 100ns. Modelling techniques based on scalable Y1 perovskyte ferroelectric materials with a lifetime exceeding 1013 programming cycles are used to demonstrate the feasibility of a system-on-a-chip approach.


TECHNOLOGY DIRECTIONS:
NEURAL NETWORKS

Chair: W. Yang, Harvard University, Cambridge, MA
Associate Chair: J. Cressler, Auburn University, AL

4.5 A Sparse Memory-Access Neural-Network Engine with 96 Parallel Data-Driven Processing Units (3:45)

K. Aihara, O. Fujita, and K. Uchimura
NTT LSI Laboratories, Atsugi, Japan

This chip has a peak performance of 30GConnections/s, contains 96 parallel data-driven 22b processors with 12,228 (16b) synapse weights, and utilizes techniques to reduce synapse-weight memory accesses and neuron calculations without reducing accuracy. In a pattern-recognition example, practical performance of 18GConnections/s was achieved.


4.6 Analog CMOS Implementation of High-Frequency Least-Mean-Square-Error Learning Circuits (4:15)

F. Kub, E. Justh
Naval Research Laboratory, Washington, DC

A continuous-time analog CMOS adaptive processor circuit that implements the least-mean-square (LMS) adaptive learning algorithm demonstrates 80MHz operating frequency, 60dB adaptivity, 25kHz notch width, 20ms adapt time constant, and simultaneous cancellation of two CW interferers.


Conclusion (4:45)

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