A 0.5mm CMOS fibre-channel transceiver includes 2 phase-locked loops for clock/data recovery at 1062Mb/s. The phase detector circuit allows the VCO to operate at 1/2 the baud rate (531MHz). VCO phase noise is 9.8ps RMS. Differential ECL I/O buffers are included in the 3.9x4.5mm2 chip. Power dissipation is 1.2W at 3.6V.

2.2 3.5Gb/s x 4Ch Si-Bipolar LSIs for Optical Interconnections N. Ishihara, S. Fujita,

A 0.5mm 40GHz Si-bipolar transmitter and receiver chip set includes 5:1 multiplexer, 1:5 demultiplexer, and analog PLL to generate 3.5GHz clock and retimed data. The set has14Gb/s throughput converting 20 700Mb/s pairs of electrical ports into 4 3.5Gb/s serial streams. 4.5mm2 transmitter and 4.5mm2 receiver dissipate 2.5W and 3.6W, respectively with -4.5V and -2V supplies.

2.3 1.65Gb/s 60mW 4:1 Multiplexer and 1.8Gb/s 80mW (2:30)

A 1.2mm 17GHz Si-bipolar chip set achieves the lowest power-delay product for a mux/demux reported to date. A current-mode-logic level- scheme reduces collector-emitter voltage for 2V operation. The mux and demux cores occupy 0.132mm2 and 0.168mm2, respectively and operate from a -2V supply.

Break (3:00)

2.4 A 900Mb/s Bidirectional Signalling Scheme (3:15)

A 0.6mm CMOS line-driver circuit has an output impedance matched to the transmission line to avoid external termination resistors. A difference amplifier decodes the 3-level line waveform by subtracting the outgoing logic state. At 450MHz clock rate, 900Mb/s of bidirectional throughput is achieved over several inches of PC board.

2.5 A CMOS Gate Array with 600Mb/s Simultaneous Bidirectional I/O Circuits (3:45)

A 0.5mm 4-layer-metal CMOS 610k gate array incorporates 608 I/O circuits and achieves a throughput of 600Mb/s per pin. A digitally-controlled-output-impedance driver uses only nMOS pull-up and pull-down devices for accurate impedance control. Power dissipation is 12mW per pin at 100MHz.

2.6 A GaAs Low-Distortion Variable-Attenuator IC for Digital Mobile Communication Systems (4:15)

An RF-attenuator chip uses octal-gate MESFET structures as voltage-variable resistors to achieve -50dBc intermodulation distortion at 0dBm input power. 25pF Barium-Strontium-Titanate capacitors used with bond-wire inductance provide input-impedance matching. The 1.05x0.9mm2 chip achieves 20dB attenuation and -30dB return loss over a 3GHz bandwidth.

2.7 150/30Mb/s CMOS Non-Oversampled Clock- and Data-Recovery Circuits with

Two 0.9mm CMOS chips achieve jitter-free clock and data recovery for burst-mode data with instantaneous locking at data rates between 50-170Mb/s and 20-70Mb/s. The chip achieves jitter rejection by resynchronizing the output data with a stable local oscillator. The 3.2mm2 and 3.7mm2 chips dissipate 30mW and 70mW at 5V including ECL-compatible output drivers.

Conclusion (4:45)

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