This SPARC V9 processor is a multi-chip module consisting of 64b CPU, memory-management unit, clock generator, and four cache-memory chips. The processor issues up to four instructions per cycle and completes up to nine. The CPU tracks 64 outstanding instructions, and uses register renaming and dataflow execution. Performance exceeds 256 SPECint92 and 330 SPECfp92.

10.2 A 93MHz, x86 Microprocessor with On-Chip L2 Cache Controller (2:00)

A 3.5M-transistor x86 microprocessor in 0.5mm CMOS uses a RISC core and a dedicated L2 cache bus. Full-custom, standard-cell, 5-layer-metalization and flip-chip-assembly technology yield a 14.1x14.1mm2. die. The chip operates at 93MHz with a 4.0V supply.

10.3 133MHz 64b Four-issue CMOS Microprocessor (2:30)

A 133MHz 64b RISC quad-issue superscalar PowerPCTM microprocessor using a 5-stage pipeline at includes six independent execution units, memory management, split 8-way associative 32kB I and D caches, and on-chip lookaside L2 cache controller. The 7M-transistor chip in 0.5mm CMOS technology has 4-level metal on an 18.2x17.1mm2 die.

Break (3:00)

10.4 A 0.6mm BiCMOS Processor with Dynamic Execution (3:00)

An Intel-architecture processor is implemented in a 0.6mm 4-layer-metal BiCMOS process. Performance improvement is achieved through a generalized dynamic-execution microengine.

10.5 A 64b Microprocessor with Multimedia Support (3:45)

A quad-issue, 4.2M-transistor microprocessor operating at 167MHz is implemented in a four-layer-metal, 0.5mm CMOS. Dedicated hardware provides up to 10x acceleration of video compression/decompression and texture-mapped 3D triangles. Custom-designed megacells and synthesis techniques provide early feedback of chip timing and die size.

10.6 A 1.2W, 66MHz Superscalar RISC Microprocessor for Set-Top, Video Game, and PDA (4:15)

This 3.3V 0.5mm 4-level metal PowerPCTM microprocessor consists of 1M transistors in a 7.07x7.07mm2 die with a power consumption of 18mW/MHz at 66MHz. Circuitry supports multimedia features such as graphics and speech recognition.

10.7 A 300MHz Quad-Issue CMOS RISC Microprocessor (4:45)

A 1200MIPS/600Mflops (peak) custom VLSI Alpha AXP microprocessor includes an 8kB instruction cache, an 8kB dual-ported data cache and a 96kB unified second-level cache. The 9.3M-transistor chip in 3.3V, 0.5mm, four-layer-metal CMOS measures 16.5x18.1mm2 and dissipates 50W.

Conclusion (5:15)

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