Flash Memory

Chair: J. Pathak, Consultant, Los Altos, CA
Associate Chair: A. Baker, Intel Corp., Folsom, CA

7.1 A 3.3V 50MHz Synchronous Flash Memory (8:30)

D. Mills, R. Fackenthal, K. Frary, T. Gullard, C. Haid,
S. Pudar, M. Rashid, R. Rozman, S. Sambandan, J. Tsang
Intel Corp., Folsom, CA

A 3.3V 16Mb Flash memory in 0.6mm CMOS delivers 20ns continuous access resulting in a maximum data-transfer rate of 100MB/s. It uses two-way bank interleaving with a segmented-array architecture. Programmable internal latency (PIL) provides operation from 50MHz down to dc. A low-threshold-voltage transistor allows operation at 3.3V.


7.2 A 3.3V-Only 16Mb DINOR Flash Memory (9:00)

S. Kobayashi, M. Mihara, Y. Miyawaki, M. Iishi, T. Futatsuya,
A. Hosogane, A. Ohba, Y. Terada, N. Ajika,Y. Kunori,
K. Yuzuriha, M. Hatanaka, M. Miyoshi, T. Yoshihara,
Y. Uji*, A. Matso*, Y. Taniguchi*, Y. Kiguchi*
Mitsubishi Electric Corp., Itami
*Hitachi Ltd., Tokyo, Japan

A 3.3V-only 16Mb divided-bitline NOR flash memory features 47ns random-access time and 60mW power dissipation during programming. A 256B page buffer achieves 1MB/s program data rate. The 0.5mm triple-poly, triple-well process produces a 1.4x1.35mm2 cell and 77mm2 die. Erase block is 64kB.


7.3 A 3.3V High-Density AND Flash Memory with 1ms/512B Erase and Program (9:30)

A. Nozoe, T. Yamazaki, K. Yoshida, H. Sato, T. Tsujikawa, H. Kotani,
M. Ishihara, S. Kubono, T. Tanaka, T. Kawahara, M. Kato, K. Kimura,
H. Kume, R. Hori, H. Kawamoto, T. Nishimoto, S. Shukuri
A. Ohba*, Y. Kouro*, O. Sakamoto*, A. Fukumoto*, M. Nakajima*
Hitachi Ltd., Tokyo
*Mitsubishi Electric Corp., Hyogo, Japan

3.3V 32Mb AND flash memory has a 512B sector program/erase. The 10.1x4.38mm2 die has 75ns random byte-access time, 36ns serial read time, and 1ms sector-erase time. High-repairability redundancy supports random sector replacement.


7.4 A 34Mb 3.3V Serial Flash EEPROM for Solid-State Disk Applications (10:00)

R. Cernea, D. Lee, M. Mofidi, E. Chang, W. Chien, L. Goh, Y. Fong,
J. Yuan, G. Samachisa, D. Guterman, S. Mehrotra
K. Sato*, H. Onishi*, K. Ueda*, F. Noro*, K. Miyamoto*, M. Morita*,
K. Kubo*
SunDisk Corp., Santa Clara, CA
*Matsushita Electronic Corp., Kyoto, Japan

A 34Mb Serial Flash EEPROM has an on-chip digitally-controlled-voltage scheme. The 121mm2 die has an erasable sector of 512 data bytes and 32.5 system-overhead bytes. The chip verifies while programming 242b in parallel. The 0.5mm CMOS process achieves a 2.1mm2 cell.


Break (10:30)


7.5 A 3.3V 32Mb NAND Flash Memory with Incremental-Step Pulse Programming (10:45)

K.-D. Suh, B.-H. Suh, Y.-H. Lim, J.-K. Kim, Y.-J. Choi, Y.-N. Koh,
S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-J. Yum, J.-H. Choi, J.-R. Kim,
H.-K. Lim
Samsung Electronics Co. Ltd., Korea

The 0.5mm 3.3V-only 32Mb NAND flash memory features a 94.9mm2 die. Incremental-step-pulse programming achieves a 2.3MB/s program data rate. A 25ns burst cycle produces a 24MB/s read data rate with an operating current less than 8mA.


7.6 A 35ns cycle time 3.3V-Only 32Mb NAND Flash EEPROM (11:15)

K. Imamiya, Y. Iwata, Y. Sugiura, H. Nakamura , H. Oodaira,*
M. Momodomi**,Y. Ito, T. Watanabe, H. Araki, K. Narita,
K. Masuda, J. Miyamoto
Semiconductor Device Engineering Lab/* ULSI Research Center/
** Memory Division, Toshiba Corp., Kawasaki, Japan

A Flash EEPROM in 0.4mm CMOS achieves 35ns cycle time by adopting a pipeline scheme. Metal-strapped select gates and boosted word lines reduce read-access time. Multiple-block erase is realized by adopting erase block registers for each block. All functions operate with one 3.3V power supply.


7.7 A Multi-Level-Cell 32Mb Flash Memory (11:45)

M. Bauer, R. Alexis, B. Balter, A. Bashir, A. Fazio, M. Hensel,
M. Ishac, P. Ruby, S. Sweha, S. Talreja, K. Wojciechowski
Intel Corp., Folsom, Ca.

A 32Mb Flash Memory is constructed with 16M physical flash cells storing two bits in each cell. 120ns access time, 25mA active current, and 10ms/B program time are achieved. 0.6mm CMOS with a 2.0x1.8mm2 cell results in a 152mm2 die.

Conclusion (12:15)


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