This register file reduces the required pipeline length of a 154MHz 4-issue super-scalar CPU by unifying the register address-rename and data-read operations into a single cycle. Data-storage cells _include 10 read and 4 write ports in 1180mm2. Sense amplifiers use partial-cycle, full-current to reduce power.

6.2 Clock-Buffer Chip with Multiple-Target Automatic Skew Compensation (9:00)

A six-output clock chip delivers clocks with ~1ns skew to the internals of multiple ASICs. The chip corrects for its own process variations as well as remotely correcting for variations in module-etch, electrical length, and ASIC clock-buffer delay due to process, Vdd, and temperature variations.

6.3 A 2.4 GOPS Reconfigurable Data-Driven Multiprocessor IC for DSP A. Yeung, J. Rabaey (9:30)

A reconfigurable multiprocessor IC for prototyping DSP algorithms with heterogeneous data-flow patterns is realized in 1mm 2-metal CMOS. The chip contains 48 data-driven processing elements interconnected by a flexible 2-level communications network and provides 2.4GOPS peak performance at 50MHz.

6.4 A Sea-of-Gates FPGA (10:00)

A 6k gate sea-of gates (SOG) FPGA in 0.7mm CMOS with 3 metal layers has an amorphous silicon antifuse (micro via) between second- and third-layer metal. The 1x1mm2 antifuse has on and off-resistances of 40W and >1GW, respectively. The device consumes 15mW at dc and 250mW at 50MHz. Programming is at 1k gates per minute.

Break (10:30)

6.5 A Fully-Integrated CMOS PLL with 15- to 240MHz Locking Range and ±50ps Jitter (10:45)

A fully-integrated PLL in 0.5mm digital CMOS has applicatons including de-skewing and frequency multiplication. The PLL core occupies 0.71mm2 and is available in a 3V, five-level-metal 1.5M gate ASIC family. Lock range is from 15 to 240MHz and output peak-to-peak jitter is <100ps at 100MHz.

6.6 An Embedded 100MIPS/W CMOS RISC Processor (11:15)

A 45MIPS RISC processor for consumer electronics operates at 50MHz and dissipates 400mW at 3.3V. The 25mm2, 400k transistor chip is implemented in 0.4mm CMOS.

6.7 Regenerative Feedback Repeaters for Programmable Interconnections (11:45)

Programmable interconnect is realized in 1.2mm CMOS using regenerative feedback repeaters. Loaded delay through a 64-pass-transistor chain is reduced by 2.2x in the clocked feedback case and 1.8x in the complementary self-timed feedback case as compared to conventional repeaters.

Conclusion (12:15)

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