Computers could be profoundly more powerful, if the interference effects possible in quantum mechanics were fully exploited. Logical primitives (the analog of AND and OR gates in classical Boolean logic) needed for a quantum computer have been established. One proposal for building these gates involves representing quantum bits by individual spin-½ particles, and executing logic on these bits using an atomic-force microscope.
19.2 A 1.5V 200MHz Pipelined Multiplier Using Multiple-Valued
Current-Mode MOS Differential Logic Circuits (1:30)
A multiple-valued current-mode MOS integrated circuit is proposed for 200MHz arithmetic systems with 1.5V supply voltage. Multiple-valued differential logic circuit and dual-rail complementary inputs results in 0.8V signal-voltage swing while providing constant drive current, so switching delay is reduced. A 1.5V 200MHz 54x54b pipelined multiplier uses 0.8mm standard CMOS.
19.3 An Integrated System Consisting of an 8x8 Adiabatic-PPS
Measured results of an integrated adiabatic (energy-conserving) system consisting of a tank circuit and an 8x8 adiabatic-pulsed-power-supply (pps) multiplier are presented. The interaction of the clock and a tank circuit converts a dc voltage to an ac sinusoid that powers the multiplier. The adiabatic system uses 20% less power than a conventional CMOS multiplier. Oscillation of the tank circuit can be stopped to save power during standby, while preserving state.
19.4 50% Active-Power Saving
A substrate bias applied in standby mode to increase the threshold voltage results in standby-power reduction (SPR). In an active mode, substrate bias is not applied for high-speed operation. An SPR circuit uses 0.3mm CMOS. Lowering both supply voltage and the threshold voltage reduces active power by 50% while maintaining speed and standby power.
19.5 Clocked-Neuron-MOS Logic Circuits
A clocked circuit using auto-threshold-adjustment for neuron MOS (nMOS) logic circuits results in enhanced noise margins. The functionality of a nMOS gate is enhanced by gate-level data subtraction. Reduced-power operation is achieved using a sense amplifier in the pipelined nMOS logic gate.
Conclusion (3:00)
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